搜索资源列表
Mul8
- 32位的加法器的实现，可以借鉴学习用于交作业-32-bit adder realization，Can be used for reference to study assignments, etc
add32
- 32位快速加法器，可硬件实现32位快速加法，效果不错-32 fast adder can be implemented in hardware rapid addition of 32, good results
code
- 32位全加器 使用verilog写的硬件描述语言，xilinx芯片上运行过-32bits full adder
Adder32Bit
- Adder 32 bit in MIPS microprocessor.
cla32
- verilog code for cla 32 bit adder
32bit_pipeline_adder
- 基于HSPICE的32位流水线加法器设计-HSPICE-based 32-bit pipelined adder design
rca_32bit
- 32 bit ripple carry adder, 32 bit rca
Vhdl-Implementation-of--Fast-32x32-Multiplier-Bas
- The Vedic mathematics is quite different from conventional method of multiplication like adder and shifter. This mathematics is mainly based on sixteen principles. The multiplier (referred henceforth as Vedic multiplier) architecture base
lab7
- 利用verilog语言设计32位进位选择加法器。实现高速计算功能。-Use verilog language design 32 carry select adder. High-speed computing.
con_addr_32
- 因为二进制加法的进位只可能是1或0，所以可以将32位加法器分为8块（最低一块由4位先行进位加法器直接构成，其余加法结构都采用先行进位加法器结构）分别进行加法计算，除最低位以外的其他7块加法器结构各复制两份，进位输入分别预定为1和0。于是，8块加法器可以同时进行各自的加法运算，然后根据各自相邻低位加法运算结果产生的进位输出，选择正确的加法结果输出。-Because binary adder carry only be 1 or 0, so it can be 32-bit adder is div
src
- 32位加法器,verilog HDL，初级用，-32-bit adder, verilog HDL
Fibonacci-sequence
- 此程序为C++语言的程序，可以输出斐波那契数列，特点是采用线性表的数据结构处理加法运算，对每一位数进行运算，并进位，解决了由于int或long int甚至unsigned long int(0~2^32-1=4294967295)的精度范围限制，此算法的精度范围主要受项数n(int)的范围(1~2^31-1=2147483647)影响-This program is C++ language program, you can output the Fibonacci sequence, is c
32ADD
- 32位超前进位加法器，verilog hdl代码实现，包含源程序-32 lookahead adder, verilog hdl code, including source code
32bitvhdl
- 基于硬件描述语言的通过加法器实现的32位乘法器-Hardware descr iption language implemented by the adder 32 of the multiplier
EDA
- 1.八进制计数器 2.八位右移寄存器 3.八位右移寄存器（并行输入串行输出） 4.半加 5.半加器 6.半减器 7.两数比较器 8.三数比较器 9.D触发器 10.T触发器 11.JK1触发器 12.JK触发器 13.三位全加器 14.SR触发器 15.T1触发器 16.三太门 17.有D触发器构成的6位2进制计数器 18.带同步置数的7进制减法计数器（6位右移寄存器） 19.二十四进制双向计数器 20.二选一 21
32bit_add
- 32位进位选择加法器 用四位先行进位加法器扩展成32位二进制加法器-32 carry select adder Used four carry-lookahead adder extended to 32-bit binary adder
Adder_Array
- 用verilog 实现了一个加法器阵列的计算，32位，位数可以扩展。-Verilog achieved by calculating an adder array 32, the median can be extended.
csa_32
- The folder gives the 32 bit carry adder chain. IN CSA for cin = 1 or 0 ripple carry adders are used.-The folder gives the 32 bit carry adder chain. IN CSA for cin = 1 or 0 ripple carry adders are used.
complexadder
- 32位复数加法器，利用ISE里的float IP核-32 complex adder, using the ISE in the float IP core
carry_select_adder(CSA)
- 32 bit carry adder can add two 32 bit numer working i have checked and simulater.32 bit carr y adder can add two 32 bit numer working i have checked and simulater.32 bit carry adder can add two 32 bit numer working i have checked and simulater.-32 bi