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vhdl_fir
- 这是一个vhdl语言写的fir filter,包括receiver, filter, transfer,可用于驱动fpga等板子-this is a fir filter use VHDL language, include receiver, filter, transfer. can be used to drive fpga and some else boards
VHDL
- 基于FPGA的IIR滤波器的各模块VHDL程序- such as in science and project technique. Compared with FIR digital filter, IIR digital filter can get high selectivity with low factorial.
FIRlvboqide-VHDLyuandaima
- 基于FPGA的通用FIR滤波器的VHDL的源代码-Based on FPGA general of FIR filters of VHDL source code
firfilt
- FIR滤波器verilog源代码,经过fpga验证可以被综合。-FIR filter verilog source code, fpga verification can be integrated.
filter_dds_10.29_7.2
- 一个经过处理的FIR filter, verilog HDL实现在FPGA上-One new design of digital FIR filter , which can be implemented in FPGA kit
ISE_IP_FIR_FPGA
- 利用ISE的IP核在FPGA上设计fir滤波器-Fir filter IP core on FPGA design using the ISE
MATLAB_FPGA_FIR
- 一种基于MATLAB及FPGA的FIR低通滤波器的设计与实现-FIR low-pass filter based on MATLAB and FPGA Design and Implementation
HalfbandDec
- 基于FPGA开发的11阶半带升余弦FIR滤波器,用在阅读器基带滤波时的抽取滤波器使用,采用verilog语言实现。-Raised cosine FIR filter based FPGA development 11 order of half-band decimation filter used in reader baseband filtering, using verilog language implementation.
DAbx
- 基于FPGA的并行FIR数字滤波器的实现-FPGA-based parallel FIR digital filter implementation
da_fir
- 基于FPGA分布式算法FIR滤波器verilog代码 (本人 小论文 代码,通过验证) 本文提出一种新的FIR滤波器FPGA实现方法。讨论了分布式算法原理,并提出了基于分布式算法FIR滤波器的实现方法。通过改进型分布式算法结构减少硬件资源消耗,用流水线技术提高运算速度,采用分割查找表方法减小存储规模,并在Matlab和Modelsim仿真平台得到验证。 为了节省FPGA逻辑资源、提高系统速度,设计中引入了分布式算法实现有限脉冲响应滤波器(F
FirFullSerial
- 15阶低通,具有线性相位的全串行FIR滤波器结构的fpga实现-15-order low-pass, with a linear phase FIR filter structure full serial fpga implementation
FIR5
- FPGA基于FIR的滤波,EP2C8芯片 40Mhz的采样频率,50KHz的截止频率的低通滤波,自己调试可用-FPGA-based FIR filter, EP2C8 chip 40Mhz sampling frequency, 50KHz cutoff frequency of the low pass filter, own debugging available
fir_test
- 采用xilinx进行的FPGA的FIR滤波器设计-Conducted using xilinx FPGA FIR filter design
FIRverilog
- 多种FIR滤波器的verilog语言实现 (数字信号处理的FPGA实现)-Verilog language variety FIR filter implementation (digital signal processing FPGA implementation)
fir_digital
- 本文对数字基带信号脉冲成型滤波的应用、原理及实现进行了研究。首先介绍了数字成型滤波的应用意义并分析了模拟和数字两种硬件实现方法,接着介绍了成形滤波器设计所需要MATLAB软件,以及利用ISE system generator在FPGA上进行滤波器实现的优势。文中给出了成形滤波函数的数学模型,讨论了几种常用成形滤波函数的传输特性以及对传输系统信号误码率的影响。然后介绍了本次设计中使用到的数字成形滤波器设计的几种FIR滤波器结构。把各种设计方案进行仿真,比较仿真结果,最后根据实际应用的情况并结合
filter_2d
- XILINX ISE FILE FOR FPGA IMPLIMENTATION OF 2D FIR FILTER USING MODIDIED BOOTH ALGORITHM
fir_verilog_matlab
- 本设计是基于FPGA的一个FIR低通滤波器设计,要求使用Verilog语言编写滤波器模块,通过编译和综合,并通过Matlab和modelsim联合仿真验证设计结果。-This design is a FIR low-pass filter design based on FPGA, use Verilog to program filter module, and joint simulation by Matlab and modelsim to validate the design re
32FIRVHDL
- 基于FPGA的32阶FIR数字滤波器设计 源程序。设计使用了并行乘法器,运行速度更快,占用内存更小,延迟更小。 -32 order FIR digital filter based on FPGA design source program. Design USES parallel multiplier, faster and less memory, less delay.
FPGA--FIR--bishe
- 一篇参考的毕业设计论文,做的是参数可调的数字滤波器。有详细的原理介绍,设计源程序及仿真流程与结果-A reference of the graduation design paper, adjustable parameters of digital filter. Have detailed introduces, the principle of the design source program and the simulation process and result
fir18
- 介绍了一种基于FPGA和高精度A/D转换器结合的FIR滤波器电路系统,该滤波器采用乘法累加器算法,并利用X ilinx公司XC3S500E的FPGA进行试验验证,主要包括对输入的正弦波信号进行A/D转换后进行滤波,通过上位机显示滤波结果。 -Introduces an FPGA-based FIR filter circuit systems and high-precision A/D converter combined, the filter algorithm using multipl