搜索资源列表
FPGAREAL
- 信号处理FPGA实现参考,IEEE transaction 的一篇文章。主要针对信号处理中加窗、FFT、VSLI快速实现中误差地等问题。-FPGA realization of a reference signal processing, IEEE transaction of an article. Mainly for signal processing windowing, FFT, VSLI rapid error problems.
FPGA_jiaocheng_yu_shiyan
- 最重要的是七个从简单到复杂的实验,包括:基础实验一_FPGA_LED 基础实验二_seg7实验以及仿真 基础实验三_SOPC_LED 基础实验四_Flash烧写 基础实验五_定时器实验 基础实验六_按键以及PIO口中断实验 实验七_网卡使用 ,这些实验室用到了SOPC BUILDER 与NOIS ii ,使用Verilog 编写,有实验板和没有实验板的都可以用来学习。 其次还包括: FPGA开发板各存储器之间的联系、 多处理器文档 、 USB_UART等文档,很好用的文档,您下了相信不会后悔!-
VHDL_DMF
- Vhdl实现扩频通信匹配滤波器,书上打下来的,打了好久.-VHDL realization of spread spectrum communication matched filter, books, playing down, playing for a long time.
write_rd
- 关于VHDL的 关于DSP的 emif-On VHDL on the DSP s EMIF
photo_verilog
- verilog开发的电子相册系统,是基于Altera的FPGA芯片和IP核的设计!-Verilog developed electronic album system is based on Altera s FPGA chip and IP core design!
FPGAkaifashilidaohang
- 《FPGA数字电子系统设计与开发实例导航》的配套光盘,Verilog编写,USB、I2C、MAC的接口设计-"FPGA digital electronic system design and development examples navigation" matching discs, Verilog prepared, USB, I2C, the MAC interface design -err
VHDL
- 采用VHDL语言设计一个4通道的数据采集控制模块。系统的功能描述如下: 1.系统主时钟为100 MHz。 2.数据为16位-数据线上连续2次00FF后数据传输开始。 3.系统内部总线宽度为8位。 4.共有4个通道(ch1、ch2、ch3、ch4),每个通道配备100 Bytes的RAM,当存满数据后停止数据采集并且相应通道的状态位产生报警信号。 5.数据分为8位串行输出,输出时钟由外部数据读取电路给出。 6.具备显示模块驱动功能。由SEL信号设置显示的通道,DISPLAY
sin.tar
- 神奇的sin波生成verilog源码,非常简单的代码无需乘法即可生成sin,cos,值得搞算法的人借鉴-Magic sin wave generated Verilog source code, the code is very simple multiplication can be generated without sin, cos, worthy people from engaging in algorithm
RGBtoYCbCr
- 采用FPGA实现色彩空间转换R’G’B’ to Y’CbCr的VHDL和verilog源代码,支持xilinx的各种器件. -FPGA realization of the use of color space conversion RGB to Y CbCr of VHDL and Verilog source code, to support a variety of Xilinx devices.
FPGA_FFT
- 基于FPGA的高速FFT处理器的设计与实现-FPGA-based high-speed FFT Processor Design and Implementation
Avalon_VGA_Controller
- Vga Controller source code for Altera FPGA
VERILOG_VERSION_PIC16C57
- VERILOG VERSION PIC16C57 是一个用于FPGA模拟PIC16C57的IP核,有帮助文件,介绍了如何测试使用这个IP核。用VERILOG语言编写的。-VERILOG VERSION PIC16C57 is a PIC16C57 for FPGA simulation of the IP core, has helped document describes how to test the use of the IP core.
AlteraSDR-SDRAM
- Altera 官方提供的SDRAM控制器,verilog的-SDRAM controller provided by Altera in Verilog HDL
v2c5_sopc_leds
- 在quartus II软件中,通过Verilog实现FPGA对于彩屏LED的控制-In quartus II software through Verilog for FPGA implementation of control LED color
Music_LiangZhu
- FPGA音乐试验,语言:verilog HDL-A FPGA expperientation which can play music Liangzhu,language:verilog HDL
FPGA_based_infrared_receiver_module
- 基于FPGA的红外接收模块,内含代码,采用VERILOG编写。-FPGA-based infrared receiver module, containing the code prepared by the use of Verilog.
CCD_DRIVER
- verilog HDL语言,线性CCD1501D驱动程序,基于FPGA,其他线性传感器可参照修改。-verilog HDL language, linear CCD1501D driver, based on the FPGA, the other linear sensor can be modified by reference.
RAM
- 用VerilogHDL写的ram程序,对初学者会有帮助。-Writing the ram with VerilogHDL procedures will be helpful for beginners.
clock
- 用verilog实现的数字跑表,下载到FPGA开发板上验证通过。下载后从新分配引脚即可用。-Verilog implementation using digital stopwatch, download to FPGA development board to verify the adoption. After the download you can use the new distribution of pins.
FPGA_radar
- 优秀硕士论文,基于FPGA的雷达信号模拟器设计,对学FPGA的,特别是学雷达的同学有很好的参考价值-Outstanding master s thesis, based on radar signal simulator FPGA design, FPGA-on study, in particular the study of radar has a good reference Student Value