搜索资源列表
verilog_dpll_
- 该源代码是用FPGA实现数字锁相环的逻辑，有需要的可以借鉴参考一下。-The source code is to use FPGA implementation of digital phase-locked loop logic, those in need can draw reference.
ddr_sdr_latest.tar
- 一款DDR400的驱动程序，使用VERILOG语言，在LATTICE—ECP2m的FPGA芯片中实际测试。-A DDR400 driver, using VERILOG language, LATTICE-ECP2m actual test of the FPGA chip.
crc16_8
- crc16,数据位宽为8，verilog编码-crc16 ,datawidth is 8,coding by verilog
x3cs400_uart
- 基于X3cS400的串口通讯程序，开发环境ISE7.0，使用verilog编写。可以使用串口调试助手在pc机上查看字符。-UART communication program based on X3CS400 FPGA， develop enviroment： ISE7.0，completed by verilog。 The result could be seen on the Uart debug assitant.
Downloads
- clock divider in verilog for FPGA use
lcd
- FPGA控制lcd1602(verilog)-FPGA control lcd1602 (verilog)
rsa
- FORFPGA IMPLEMENTATION OF RSA ALGORITHM USING HDL
sobel_filter
- implementation of SOBEL filter using FPGA board RC200 in handle-c
TLC5620
- Verilog HDL语言，FPGA实现TLC5620的DAC源代码-Verilog HDL language, FPGA implementation of the DAC TLC5620 source code
TLC5510
- 采用超高速AD存储示波器程序设计。器件是采用TLC5510。用FPGA来控制实现。-The ultra high speed AD storage oscilloscope programming. Device is used TLC5510. Using FPGA to control the implementation.
eda
- 利用FPGA可编程芯片及Verilog HDL语言实现了对直流电机PwM控制器的设计，对直流电机速度进行控制。介绍了用Verilog HDL语言编程实现直流电机PwM控制器的PwM产生模块、串口通信模块、转向调节模块等功能，该系统无须外接D／A转换器及模拟比较器，结构简单，控制精度高，有广泛的应用前景。同时，控制系统中引入上位机控制功能，可方便对电机进行远程控制。-Using FPGA programmable chip and Verilog HDL language for the desi
clk_divider
- Simple Clk Divider for FPGA design in Verilog -Simple Clk Divider for FPGA design in Verilog
uart1
- RS232(UART)串口传输，通过了FPGA验证功能正确-UART RS232 verilog HDL FPGA xilinx
goip
- This application is about xinlinx fpga. initialize the gpio,led,switch and others in the college project board. If you are a novice, this application will help you shorten the learning time.
MyDDS
- 利用查找表法编写的DDS的verilog程序，节省了利用IP核实现需要的资源，软件为ISE，-Prepared using look-up table method of verilog DDS program, save the use of IP core implementation requires resources, software for the ISE,
HDB3
- 采用FPGA产生数字基带系统传输码型HDB3码，采用《通信原理》例子设计。-Generated by FPGA digital baseband transmission code HDB3 code system, a " communication theory" example design.
564-784-fpga-1-develop
- 该文档主要针对Verilog语言的快速应用指南，包括语法、综合及硬件方面的应用等内容-The document aimed at the rapid application of Verilog language guide, including grammar, comprehensive and content of the application of hardware
VerilogFPGAUSB
- 用Verilog（FPGA）实现USB源代码大家-Using Verilog (FPGA) source code we look to achieve USB
Fre_Counter_verilog
- 基于ep3c25的FPGA频率计的简单设计（用verilog HDL），直接打开即可-FPGA frequency counter based on ep3c25 of simple design (using verilog HDL), can directly open the ... ...
kj
- FPGA环境下学习用verilog hdc编程，可快速入门 的ppt-FPGA environment for learning programming with verilog hdc, fast entry of ppt