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led2
- nios ii 流水灯源程序,采用quartus ii 11.0,nios ii 11.0,qsys构建CPU,由本人亲自编写,并下载至电路板验证流水灯成功-nios ii water lights, quartus ii 11.0 nios ii 11.0 qsys build the CPU, I personally prepared and downloaded to the board verification of light water
11111
- 1、用FPGA/CPLD实现HS162字符液晶显示。 2、分析相应的功能要求,分析CPLD与字符液晶HS162的接口典型电路。 3、利用状态机的设计方法,通过指令编程实现对HS162-4液晶模块的读/写操作,以及屏幕和光标的操作。 4、编写模块的Verilog HDL语言的设计程序。 5、在Quartus II软件或其他EDA软件上完成设计和仿真。 -This design of a CPLD-based controls HS162 to achieve character
plot_f1
- 此程序的功能是对Quartus II软件仿真完成之后,导出的.tbl文件进行matlab画图,画出其时域图和频域图。其中待处理的.tbl文件,我将其进行人工处理,手动删除了无用信息,只剩余时间点、输入信号和输出信号。-The function of this program after the completion of the Quartus II software simulation, export tbl file matlab drawing, draw a diagram of th
frequency-meter
- 开发环境是quartus ii,是学校的一个FPGA实验,计算一个信号的频率,这个是我做得最好的一个作品,调试成功。压缩包里包含题目要求以及我做好的模块。-Development environment is quartus ii, an FPGA experimental school, calculate the frequency of a signal, this is I' m doing the best work, debugging success. The compres
ALTERA-advanced-part-CD-ROM
- 配套光盘提供了书中所有示例的完整工程文件、设计源文件和说明文件。 每个工程示例都包括了该工程的项目文件、源文件、报告文件和生成结果等文件,读者可以用Quartus II或相应的软件直接打开。设计源文件根据设计输入类型分为源代码或原理图等。请读者将设计源文件拷贝到计算机硬盘上,并按照书中的操作步骤自行操作练习。示例说明文件包含了示例的详细信息和操作指南。 通过对本书的学习,读者对图1所示的Altera常用开发工具都有了一定的认识,可以说本书的核心内容就是讨论Altera Quartus I
BARK-xuhuanmafinal
- 简单的quartus循环码设计,中间加入了BARK码帮助同步。希望对大家有所帮助。-Simple the quartus cycle code design, joined in the middle BARK code to help synchronize. I hope to be helpful to everyone.
fdivision
- 一个分频的quartus工程,用verilog写的,改变i的值可以实现任意分频,绝对原创-Quartus project a divide verilog write, change the value of i can achieve arbitrary divide absolute originality! ! !
dianliuyuanMSP430
- 基于MSP430系列单片机的直流电流源,quartus软件vhdl编程仿真的,里面含程序 并附有实物图,我呕心沥血之作-Based on MSP430 MCU DC current source, quartus software VHDL programming simulation, which contains the program together with the physical map, I worked hard to make
jiaotongdeng
- 本程序采用quartus新版本制作,本人亲测可用,是我们课程设计要求的交通灯经典程序,由小组成员共同开发,实现主干路与支路同步计时。-This procedure uses a new version quartus production, I pro-test available is our curriculum design requirements of traffic lights classic program, jointly developed by the team membe
zuoyepaoma2
- 基于FPGA的跑马灯设计,可实现一个灯独跑,两个灯连跑,间断跑,隔着2个灯跑自定义跑灯形式。quartus软件亲测可用,自己编写的~-Marquee FPGA-based design can achieve an independent running lights, two lights Lianpao, intermittent run, run across two lights running lights in the form of custom. quartus software
reg_8_io_clrset
- ALTERA NIOS处理器实验,QUARTUS下用VHDL编译成处理器,reg的io口软件-Altera NIOS processor experiments QUARTUS using VHDL compiler into processor, the io I reg software
SSRAM_250M
- 本人编写的SSRAM高速读写工程,工程中包含了NIOS软核,利用Quartus的TimeQuest工具进行了时序约束,上班调试最高读写速率可达250MHz。-I write the SSRAM high-speed, speaking, reading and writing, engineering includes NIOS soft core, timing constraint is studied by using Quartus TimeQuest tools, work to de
nios_ruanhe_spi_3
- 这是我自己写的一个摄像头数据存储SD卡程序,quartus的verilog编写,摄像头采用自己添加的外设接口,数据采用dma采集,SD用的是软件自带的SPI内核以及znFAT的文件系统。帧率我没有测,有兴趣的可以测测,初学者可以参考学习,写的代码有点乱,如果有不懂的可以和联系。-This is what I wrote it myself a camera, SD card data storage program, quartus the verilog write, add their ow
taxivalue
- 我用FPGA来实现,这是一个出租车计价器,用来计算里程,我已在Quartus 2实现。-I used the FPGA to achieve, this is a taxi meter, calculate the mileage, I have been in quartus 2 to achieve.
20161203_ii
- MD5认证部分的第四轮中包含I函数的一次操作的FPGA实现源代码,采用Verilog,在Quartus II上综合-The fourth round MD5 authentication section contains FPGA one operation I Functions of the source code, using Verilog, synthesis in Quartus II
basketball_24time1
- 该文档主要是用verilog语言实现篮球24秒计时器,这是我做的数字电子技术课程的一次大作业。 里面为整个文件夹,解压之后可在Quartus13.0上直接运行。(This document mainly uses Verilog language to realize basketball 24 second timer, which is a big assignment of digital electronic technology course I do. It contains the
Quartus_17.1_Update1破解器
- Quartus_17.1_Update1破解器quartus 17.1 安装包,我现在用的就是(Quartus 17.1 installation kit, what I am using now is)