搜索资源列表
Actel_DirectCore_CORESPI_4.2.116
- Actel DirectCore CORESPI 4.2.116 Verilog and VHDL RTL source files for SPI controller on APB
ibm_rtl
- The RTL table as presented by the EBDA.
vhdl
- 4dsp fmc150 RTL Source
ps2_soc2
- PS2 Control Verilog RTL Code
DDR2Controller
- DDR2 SDRAM Control Verilog RTL Code
des.tar
- DES Encoder and Decoder Verilog RTL Code
digital-IC-low-power-design-overview
- 一篇文章，综述数字IC从哪些方面可以降低功耗，包括版图级，rtl级，算法级，系统级等-An article, review digital IC what can reduce power consumption, including the territory level, rtl level, algorithms, system, etc.
HDB3-encoderauncoder
- HDB3编码器与解码器，以及RTL图，使用Verilog HDL实现-HDB3 encoder and decoder, and RTL diagram, use Verilog HDL to implement
8139too
- A RealTek RTL-8139 Fast Ethernet driver for Linux.
qib_6120_regs
- This file is mechanically generated RTL. Any hand-edits will be lost!. -This file is mechanically generated RTL. Any hand-edits will be lost!.
1
- AHB MASTER vhdl code and rtl schematic. dhasu code he bidu check kl lo bhle hi
sync_fifo
- 同步fifo实现代码，包括的参数：数据宽度、fifo深度、地址宽度；状态信息包括：full, empty。-verilog RTL code which implement a synchronous FIFO function with data width, fifo depth, address pointer width parameterized.
rtl_wangjiangxing
- ecc椭圆算法RTL,verilog经过验证-ecc verilog
HASH
- hash加速器的verilog实现，也用于fpga或asic-hash verilog rtl
AES
- aes源码verilog带有仿真环境，可用于FPGA实现-aes verilog rtl
pka_engine
- rsa ecc加速器源码和仿真环境，用于fpga-rsa ecc rtl and sim
Example-b4-1
- 1.定制一个双端口RAM，DualPortRAM 2.在顶层工程中实例化这个RAM 3.实现这个工程，在Quartus II仿真器中做门级仿真 在ModelSim中对这个工程进行RTL级仿真-1. Customize a dual-port RAM, DualPortRAM 2. In the top-level project instantiate RAM 3. To achieve this project, do gate-level simulator in Qua
APM-flight-control-mode-switch
- APM模式切换器功能说明，将该切换器替换原先控上的2段或3段开关，可以方便的为APM的6种飞行模式进行切换。默认设置的6中模式为 简单稳定，定高（AltHold）定点（Loiter）自动（Auto）返航（RTL）稳定（Stabilize） 这6种飞行模式是用的比较多的，可以根据自己需要设置成其他的飞行模式。-APM mode switching function descr iption, the switch to replace two or three segments segme
rtl_viterbi_veeRen
- RTL design Viterbi decoder using VHDL
antenna-effect
- 硬件电路设计中消除天线效应的电路RTL级Verilog代码-RTL grade of Verilog codes for reducing antenna effect