搜索资源列表
ADDER8B
- 用VHDL描述了八位加法器，并通过波形仿真验证其正确性-Described in VHDL eight adder and verify its correctness by means of simulation waveform
vhdl1
- 该程序实现了运用VHDL实现数字音频滤波，同时在FIR 滤波过程中减少了加法器和乘法器使用数量，大大减小了内存-The program implements the use of VHDL digital audio filtering, while in the FIR filtering process to reduce the number of adders and multipliers used, which greatly reduces the memory
JIAFA_4
- 加法器，采用流水线技术设计四级加法器，VHDL实验-Adder, four pipelined adder technical design, VHDL test
adder-8segmengt-display
- FPGA/CPLD开发，基于VHDL语言的加法器实现，并用数码管显示-FPGA/CPLD development, based on VHDL adder implementation, and use digital tube display
add
- VHDL 相应加法器的测试向量（test bench)，非常简单的。我已测试通过-VHDL equal 8-bit comparator routines, very simple. I have the test pass
excess-3-code-adder-subtructer
- 余3码excess-3 code加法器和减法器，用vhdl实现-I 3 yards excess-3 code adder and subtractor using vhdl
EDA
- 用VHDL语言实现8位移位加法器。代码简单-With VHDL 8-bit shift adder. Simple code
SHIYAN
- VHDL多个小实验，包括加法器，AD变换，状态机、波形发生器等-VHDL several small experiment includes an adder, AD conversion, the state machine, the waveform generator
add
- 在fpga上实现加法器功能，使用的是vhdl语言-Achieve sum functions on fpga
adder4
- 基于VHDL的4位加法器。 由4个一位全加器级联构成。-VHDL-based 4-bit adder. One consists of four full adder cascade.
multiply_8_VHDL
- 由8 位加法器构成的以时序方式设计的8 位乘法器，采用逐项移位相加的方 法来实现相乘的VHDL程序代码。包含几个小模块和一个顶层设计文件，运行可用。-an 8 bit multiplier combined with 8 bit adder using a design by way of timing,and it use a way of Itemized shift to implement the multiply.It include some little module and
Add_ahead
- 无流水线加法器与寄存器结合在一起的相位累加器设计程序-vhdl implementation of phase accumulator without pipelines
ImprovePipelineAdder
- 基于流水线加法器与寄存器结合在一起的相位累加器设计程序-vhdl implementation of phase accumulator with pipeline and registers.
adder
- 四位二进制串行加法器 VHDL语言 EPM240 数字逻辑实验-Four serial binary adder VHDL language EPM240 digital logic test
adder4bit
- VHDL设计的四位加法器器，仿真测试正确，可以使用。-VHDL design of four adders, a simulation test correctly, you can use
f_adder
- 利用VHDL的语言，实现考虑进位的全加器，该程序带中的加法器带有使能端，可以更好地实现所需功能。-Using VHDL language to achieve considering the carry bit full adder, the program with the adder with Enable, can better achieve the desired function.
Calculator
- VHDL计算器，涉及PS2输入，VGA视频输出，加法器，BCD转化。可以通过研究代码学习以上知识-VHDL calculator, involving PS2 input, VGA video output, the adder, BCD transformation. You can learn more knowledge through research code
shiyan_1
- 这是一个使用VHDL编写的串行加法器程序，简单易用，是初学者必备-This is a serial prepared using VHDL adder program, easy to use, is essential for beginners
32adders
- 32位加法器实现程序，VHDL/VERILOg实验课上可以直接用-32 adders to achieve program, VHDL/VERILOG
4weichaoqianjinweiqi_verilog
- 四位超前进位加法器的verilog实现。用VHDL语言，附加检验tb.v-Four lookahead adder verilog implementation. VHDL language, additional testing tb.v