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cpu
- 8位CISC模型计算机设计，包括加减法存储输出的运算-8-bit CISC model of computer design, including the addition and subtraction operations stored output
c16_latest.tar
- c16 ucore. this a 16 VHDL cpu core. complete with Assembler and C compiler. All src code included.-c16 ucore. this a 16 VHDL cpu core. complete with Assembler and C compiler. All src code included.
CPU-design
- 使用VHDL语言开发的CPU硬布线设计，在实验电路可以使用加法，和减法与或等简单操作-CPU using VHDL language development of hard-wired design, the circuit can be used in the experimental addition, and subtraction or other simple operations with
POC-Project
- 系统总线与打印机之间的借口：并行输出控制器POC的设计。涉及POC与CPU，POC与printer之间的握手操作。-Between the system bus and an excuse for the printer: parallel output controller POC design. Involved in POC and CPU, POC and the printer handshake between the operations.
CPU
- 使用VHDL语言实现了一个两级流水线的CPU，-VHDL language using a two-stage pipeline of the CPU,
cpu-design
- VHDL设计的一个可综合的精简指令集的CPU，加上外围模块，类似与51单片机，当然还缺少很多功能，只是雏形，供大家交流-VHDL design of an integrated RISC CPU, coupled with external modules, exhausted and 51 single-chip, of course, the lack of many features, but prototype for all to share
project3
- mips single cycle cpu
POC_all
- poc即为cpu与外部设备，比如打印机的接口，用VHDL的编程来实现poc功能的仿真-poc is the cpu with an external device, such as the printer' s interface, programming with VHDL simulation capabilities to achieve poc
parallel-output-controller-(POC)
- 并行输出控制器，实现CPU与打印机之间的通信，程序基于VHDL语言，内附完整实验报告与仿真图像-The purpose of this project is to design and simulate a parallel output controller (POC)which acts an interface between system bus and printer. The Altera’s Quartus II EDA tool is recommended and provid
lcdasegaled
- lcd显示 跑马灯显示 七段数码管计时 12232F是一种内置8192个16*16点汉字库和128个16*8点ASCII字符集图形点阵液晶显示器,它主要由行驱动器/ 列驱动器及128×32全点阵液晶显示器组成。可完成图形显示,也可以显示7.5×2个(16×16点阵)汉字.与外部CPU接口采用并行或串行方式控制。-lcd display Seven-Segment LED Display Marquee is a built-in timing 12232F 8192 16* 16 points
zxcpu
- 用VHDL语言设计了一个含10条指令的RISC处理器。假定主存可以在一个始终周期内完成依次读写操作且和CPU同步，系统使用一个主存单元。处理器指令字长16位，包含8个通用寄存器，1个16位的指令寄存器和一个16位的程序记数器。处理器的地址总线宽度16位。数据总线宽度16位，取指和数据访问均在一跳蝻数据总线。处理器支持包含LDA，STA，MOV，MVI，ADD，SUB，AND，OR，JZ，JMP十条指令。其中仅有LDA和STA是访存指令。-VHDL language design with a R
cpu
- 16位的5级流水线cpu 采用vhdl代码 modelsim编译仿真-5-stage pipeline 16-bit cpu compiled simulation using modelsim vhdl code
VHDL--8-bit-cpu
- VHDL实现简单的8位cpu功能，该程序代码实现cpu部分功能 -VHDL simple function of the 8-bit cpu
cpu00
- VHDL cpu MUTIPYL ADD SUB JMP SHIFTL -VHDL cpu MUTIPYL ADD SUB JMP SHIFTL
mycpu
- VHDL cpu MUTIPYL ADD SUB JMP SHIFTL -VHDL cpu MUTIPYL ADD SUB JMP SHIFTL
CPU-exp
- 基于VHDL编写的CPU程序，用微程序的方式实现。内含说明本程序的说明文档。-CPU program written in VHDL, with the micro-program ways.Containing the document of the program.
fpga
- vhdl编写的，用来模拟简单cpu的论文-vhdl cpu fpga
cpu
- algoritme tarahie cpu ba estefade az codhaye mojud dar ketabe mano be zabune vhdl
cpu
- tarahie alu ba estefade az codhaye ketabe mano be zabune vhdl
IP-code(8051-cpu-jtag-vga_lcd-i2c)
- ip核源码，包含8051,cpu,jtag,vga_lcd,i2c，使用vhdl语言编写，-ip nuclear source, including 8051, cpu, jtag, vga_lcd, i2c, using vhdl language,