搜索资源列表
voltage
- 通过FPGA 控制实现数字电压表的设计，用VHDL实现，编写源代码-FPGA control through the digital voltage meter design, the realization of VHDL, the preparation of the source code
ktf
- 这是一个用VHDL编写的占空比可调的程序，对一个刚刚入门的FPGA的学员来说可以起到一个引导作用，简单但能学到很多东西-This is a VHDL prepared with adjustable duty cycle of the process, just getting started on a FPGA for the students can play a guiding role, a simple but can learn a lot
src
- DQPSK modulation with XILINX FPGA. 2 level butterworth analog filter for I & Q D/A output. -DQPSK modulation with XILINX FPGA. 2 level butterworth analog filter for I & Q D/A output.
my_uart_top
- 实现的功能如题，就是FPGA里实现从PC接收数据，然后把接收到的数据发回去。使用的是串口UART协议进行收发数据。上位机用的是老得掉牙的串口调试助手-To achieve the functions such as title, that is, to achieve FPGA receives data from the PC, and then receive data back fat. Using a UART serial port protocol to send and recei
FFT
- FFT的资料，有很多的论文和文章。主要用于FPGA的设计-FFT data, there are many papers and articles. Mainly used for FPGA design
db0358fc-1f16-4f07-9f0f-defb77998bb1
- fpga实现简单的计数器功能，用vhdl写的，有一个LED-fpga simple counter function
fuzzy_inference
- VHDL模糊PID控制器模糊推理，推理结果：直接用经验值输出。-Fuzzy PID controller VHDL fuzzy reasoning, reasoning results: the direct use of the experience of the value of output.
ADC0809
- VHDL写的ADC0809的控制转换程序，很容易就看懂的，结构明晰，还有示波器输出模式。-ADC0809 write VHDL control the conversion process, it is easy to understand, and the structure of clarity, as well as the output mode oscilloscope.
ImplementLUT-baseFIRFilterwithVHDL
- 用VHDL语言实现查找表方法有限冲击响应滤波器-VHDL language used lookup table method to achieve finite impulse response filter
dds
- 如何利用FPGA产生DDS调频信号 很具体的-How to make use of DDS generated FM signal FPGA specific
12864
- 基于VHDL语言，控制液晶12864显示的源程序，非常好用。-Based on the VHDL language, control of liquid crystal display source code 12864, very easy to use.
ad_pll
- fpga的pll锁相设计，altera器件EP1s25的选用、设计-phase-locked pll of fpga design, altera devices EP1s25 selection, design
xapp856
- 基于FPGA的SFI接口实现（VHDL，Verilog and doc）-SFI-4.1 16-Channel SDR Interface with Bus Alignment
counter
- 适用于FPGA Xilinx开发板的Counter程序，计数从0到9999，在板上用4位7段数码管显示，可实现双向计数。-Applicable to FPGA Xilinx development board of the Counter procedures, counting from 0 to 9999, in the board with four 7 digital display, enabling two-way counts.
uart
- 基于FPGA的多调制UART的设计，相当不错，可估参考-FPGA-based multi-modem UART design, very good reference to assess
fpga
- 大量VHDL语言的实例，很多都是非常经典的例子，是我学习FPGA过程中不断积累的。-VHDL example of a large number of languages, many of them are very classic example is the process I am constantly learning FPGA accumulated.
HuaWei_FPGA_Design
- 华为FPGA设计流程说明 由于目前所用到的FPGA器件以Altera的为主，所以下面的例子也以Altera为例，工具组合为 modelsim + LeonardoSpectrum/FPGACompilerII + Quartus，但原则和方法对于其他厂家和工具也是基本适用的。-Huawei FPGA design flow as a result of the current devices used to Altera' s FPGA-based, so the following
vga
- Xilinx FPGA verilog程序,用于控制VGA接口控制CRT显示器工作，使其实现色彩条显示-Xilinx FPGA verilog procedures VGA interface control used to control the work of CRT monitors to achieve color display article
HEX2BCD
- 基于fpga的二进制和BCD骂转换模块vhdl描述，只需修改相关参数即可使用-Fpga-based binary and BCD conversion module called vhdl descr iption, simply modify the relevant parameters to use
keydecoder_deb
- 基于fpga的键盘扫描输出模块vhdl描述，可以直接调用，也可稍作修改另用-Fpga-based keyboard scan vhdl descr iption of output module can be called directly, with some slight modifications can also be separate