搜索资源列表
DDS
- vhdl编写的dds信号发生器 这是比较古老的写法,但很简单-vhdl prepared dds signal generator which is a more ancient writing, but it is simple
URAT_transmitter_receiver_VHDL
- 基于UART的VHDL程序,包括顶层程序、波特率发生器程序、UART发送器程序、UART接收器程序4部分程序。有详细注释,并在每个程序后附上一张仿真波形图,便于理解和验证。-UART in VHDL-based procedures, including the top-level procedures, procedures for the baud rate generator, UART transmitter program, UART receiver program four par
venomgen
- venomgen - C source code of VHDL code generator for CRC, BCH and RS encoder -venomgen- C source code of VHDL code generator for CRC, BCH and RS encoder * polynomials can be entered via command line * variable bus width * automatic testbench
EDA
- EDA实验:掌握使用VHDL 描述组合电路的基本方法,学会使用QuatusII 对VHDL 代码进行综合和仿真,能够使用时序仿真功能对所设计模块进行仿真测试。(四位二进制数比较器 序列信号发生器 十字路口交通灯的设计)-EDA experiment: to master the combination of the circuit VHDL descr iption of the basic methods, learn to use QuatusII of the VHDL code synt
wave_gen
- wave generator in vhdl
pmw
- 基于VHDL的pmw发生器论文格式,仿真实现。word文档-pmw,VHAL,pluse width modulation generator
plusewidthmodulationgeneratorqartus
- pluse width modulation generator。基于VHDL语言,PMW波形发生器-pluse width modulation generator VHEL
FPGA_DDS
- 基于FPGA的DDS信号发生器产生VHDL源码及其测试激励文件的matlab模型,在modelsim下仿真通过-FPGA-based VHDL source DDS signal generator and the test stimulus file matlab model simulation in modelsim adopted under
dds_quicklogic
- 关于信号发生器的VHDL编程,很好的程序,可供大家参考学习,-VHDL programming on the signal generator, a good program, for your reference study, huh, huh
renyiboxing
- 信号发生器是一种常用的仪器,能够实现各种波形,不同频率的输出,电子测试系统的重要部件。本研究 的数字信号发生器足基于直接数字合成即DDS技术设计的,采用VHDL与C语言相结合的方法,通过查找存储 于ROM查找表中的各种标准波形数据,产牛频率Hf调并且高精度的正弦波、方波、锯齿波等常用信号,并且町 以通过修改表中的数据,实现任意信号发生器-Signal generator is a commonly used instrument to achieve a variety of wav
my_gold
- 基于FPGA的gold码发生器,用VHDL语言编写的源程序。-The gold code generator based on FPGA, VHDL language with the source.
DDS
- 基于FPGA的DDS的相位累加器详细介绍,是VHDL编程,利用quartus2平台.-Design of Direct digital synthesis Signal Generator
boxing
- 多功能波形发生器完全设计源代码 VHDL语言设计 -Multi-waveform generator
VHDL_code
- 三角波发生器,VHDL代码,要的朋友下载!-Triangular wave generator, VHDL code, to be a friend to download!
zy4668_function
- 本源码的功能是用vhdl编写实现多功能函数信号发生器-The source function is written using vhdl achieve multi-function signal generator
crc-gen
- CRC Generator is a command-line application that generates Verilog or VHDL code for CRC of any data width between 1 and 1024 and polynomial width between 1 and 1024. The code is written in C and is cross-platform compatible
sine_package_256
- sine wave generator in VHDL code
PARITY
- this a parity generator which can be a straight forward code for those who are novice in vhdl
sin
- 正弦波发生器。用VHDL语言实现。基本功能。-sinusoid generator
vhd
- 波形发生器 是基于VHDL的原码;可以下载下来看看。-waveform generator for VHdl