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VHDL_Starter_Examples
- 河北大学-VHDL实验课程相关的所有VHDL源代码，含具体的工程文件和原始课件，直接可以在Quartus II打开进行仿真-Hebei University-VHDL experiments related to the course all VHDL source code, including the specific project files and original software, you can directly open the Quartus II simulation
TrafficLightsControl
- quartus II 下 VHDL语言实现交通灯的控制-quartus II vhdl Traffic Lights Control
HighSpeedParallelMultiple
- quartus II 下VHDL实现快速乘法器-quartus II VHDL High Speed Parallel Multiple
9-multiple-9
- quartus II 下 VHDL实现 九九乘法表-Quartus II VHDL 9 multiple 9
CNT10
- 通过Quartus II 软件，VHDL语言实现10进制计数器-Achieve 10 binary counter
Pingpong
- A Altera DE-2 ping pong game which using a PS/2 keyboard to control.VGA port of DE-2 will be the output of the game video.The sources code build from VHDL code on Quartus II.-A Altera DE-2 ping pong game which using a PS/2 keyboard to control.VGA por
cny24
- 24进制加法计数器适用于vhdl和quartus-24 binary adder vhdl counter applied and quartus
Quartusii11_13192
- 用于quartus，适用于vhdl、ahdl的设计，适用win7等系统-Designed for quartus, applicable to vhdl, ahdl applicable win7 systems
auto_baud_with_tracking
- ALTERA NIOS处理器实验，QUARTUS下用VHDL编译成处理器，自动band跟踪小程序-Altera NIOS processor experiments QUARTUS using VHDL compiler into processors, automatic tracking small band procedure
bcd_to_binary
- ALTERA NIOS处理器实验，QUARTUS下用VHDL编译成处理器，bcd码转bin-Altera NIOS processor experiments QUARTUS using VHDL compiler into processor, code switch bin bcd
binary_to_bcd
- ALTERA NIOS处理器实验，QUARTUS下用VHDL编译成处理器，bin转bcd-Altera NIOS processor experiments QUARTUS using VHDL compiler into processor, bin turn bcd
component_timer_counter
- Quartus环境下基于VHDL元件例化的数字钟程序-Zhong Chengxu digital VHDL component instantiation based on Quartus environment
vhdlquartusfft16
- fft16 点， quartus2 9.0 用vhdl编写各个模块，然后用电路图形式连起来 如有问题 plklklklkl@sina.com 里边还有 报告-ffft 16 quartus
fir_test01
- 在quartus ii 环境下，用VHDL语言编写的基于ALTERA 的IP核的FIR低通滤波器。 -In quartus ii environment, using VHDL language ALTERA FIR IP core based on the low-pass filter.
FPGA_QPSK_EXP
- Quartus编写的QPSK解调仿真模块，用于各个功能模块的硬件仿真使用，由VHDL语言编写，适合通信工程专业人士使用-Quartus simulation module written QPSK demodulation hardware emulation for various functional modules using VHDL language for communications engineering professionals use
huxi
- 基于VHDL设计四个频率不同的呼吸灯，呼吸频率分别为 0.1Hz,0.2Hz，0.4Hz，0.8Hz 呼吸灯原理：利用PWM波控制led的亮度，的 原始代码 quartus软件亲测可用。-VHDL-based design in four different frequencies breathing light, breathing frequency was 0.1Hz, 0.2Hz, 0.4Hz, 0.8Hz breathing light principle: the use PWM
daojishi
- 基于VHDL编写的60S倒计时，可以设置倒计时开始时间， 重置倒计时，倒计时结束数码管会闪烁，蜂鸣器报警，quartus软件亲测可用。-60S-based VHDL, countdown, countdown start time can be set, reset the countdown, countdown to the end of the LED will blink, buzzer alarm, quartus software pro-test available.
huxideng
- 基于VHDL的呼吸灯设计， 可设置4个频率分别为0.1 ，0.2，0.4 0.5MHZ，quartus软件亲测可用-VHDL-based design breathing light can be set to four frequencies were 0.1, 0.2,0.4 0.5MHZ, quartus software pro-test available
myfir
- VHDL设计的FIR滤波器，有Matlab设计文件，Quartus II工程以及Modelsim仿真结果和说明文件-VHDL design FIR filters, Matlab design documents, Quartus II project and Modelsim simulation results and documentation
2freq_uart_se
- 高精度串口频率计VHDL源码，开发环境为Quartus II 9.0，频率范围为0-1MHz-Precision frequency meter serial VHDL source code, development environment for Quartus II 9.0, the frequency range of 0-1MHz