搜索资源列表
I2C
- 用verilog HDL实现I2C Master Controller 的设计，包括主程序设计和测试程序设计-Verilog HDL using I2C Master Controller to achieve the design, including the main program design and test program design
testbench
- 利用system verilog写仿真测试程序，详细介绍system verilog的语法，及教程 -use system verilog write testbench
multiply
- Verilog hdl语言 常用乘法器设计，可使用modelsim进行仿真-Verilog hdl language commonly used multiplier design, can use the ModelSim simulation
I2C_rw
- 读写I2C FLASH的Verilog程序 -The Verilog program to read and write I2C FLASH
verilog
- Verilog桶形移位寄存器，实现不溢出移位-Verilog barrel shift register, the shift towards non-overflow
I2C_Slave
- I2C从设备（Slave） Verilog 代码、设计文档和使用文档，简单、适用：很方便修改工作频率，自定义寄存器接口。-I2C slave (Slave) Verilog code, design documents and user guide, simply to apply: the frequency of easy modification, customized register interface.
dds
- 基于FPGA的DDS设计，本程序采用verilog HDL语言编写，使用DDS+Pll倍频-The DDS-based FPGA design, the procedures used verilog HDL language, the use of DDS+ Pll frequency
DDS
- DDS文件夹内的程序，完成直接数字频率合成功能,有正弦,三角,方波三种波形,并能扫频. 可通过键盘操作设置频率参数和选择波形种类和控制运行. 由两部分组成,"C"文件夹内,是用于在 51 单片机上运行的 C语言程序, "Verilog"文件夹内,是用Verilog语言编写的 FPGA 程序.-DDS program folder, complete direct digital frequency synthesis function, sine, triangle, square
jtag_uart
- 用verilog 语言写的jtag_uart程序用于实现jtag的串口通信-Using verilog language written in jtag_uart procedures used to implement the serial communication jtag
SDRAM
- SDRAM控制器，Verilog代码编写，让你快速了解SDRAM的读写时序。包含Modelsim仿真工程和学习笔记-SDRAM controller, Verilog coding, allows you to quickly understand the SDRAM read and write timing. Modelsim simulation engineering and contains study notes
RS-code
- 我测试过的！Verilog HDL实现RS编码。-I' ve tested it! RS coding Verilog HDL implementation.
viter2
- verilog实现卷积码的译码，viterbi算法-verilog to achieve the decoding convolutional codes, viterbi algorithm
ug_ram
- RAM design for FPGA in verilog
UART
- 语言：verilog语言 功能：通过串口控制模块，实现FPGA与串口 通信。 仿真环境：modelsim 综合环境：quartus -Language: verilog language function: through the serial port control module, FPGA and serial communication. Simulation Environment: modelsim integrated environment: quartu
IEEE_Verilog_2001
- Verilog 2001 编程规范，作为ASIC和FPGA逻辑开发人员学习不可多得的资料，也可以作为逻辑开发高手们学习查阅的工具。新手们可以按照实例自己编程操练。
beep
- verilog写的控制喇叭的FPGA程序。-written in Verilog FPGA speaker control procedures.
FINALWORK
- 简易信号发生器 可产生正弦波、方波、三角波、锯齿波 周期可调 verilog-Simple signal generator can produce sine, square, triangle wave, sawtooth-cycle adjustable verilog
shuzizhong
- Verilog写成的数字钟 可以在ISE或者quartus环境下运行仿真-Verilog digital clock can be written in the ISE environment or running simulation quartus
DDS
- 基于DDS原理的正弦信号发生器。用VERILOG语言实现，功能强大。-DDS based on the principle of sinusoidal signal generator. Using Verilog language and powerful.
CPU
- 一个多周期CPU的完整设计，quartus平台，Verilog实现，内含实验报告，和详细的各模块功能表-Complete a multi-cycle CPU design, quartus platform, Verilog implementation, includes lab reports, and a detailed menu of each module