搜索资源列表
DigitalWatch
- Digital watch write in Verilog HDL language simulate the real clock in Atera DE2 development board
msk
- msk调制verilog HDL 实现，对学习微电子的人很有帮助-msk modulation verilog HDL to achieve, people very helpful in learning Microelectronics
verilog_tutorial
- Chapter 1 Introduction Chapter 2 History of Verilog Chapter 3 Design and Tool Flow Chapter 4 My First Program in Verilog Chapter 5 Verilog HDL Syntax and Semantics Chapter 6 Gate Level Modeling Chapter 7 User Defined Primitives Chapter
verilog
- 华为的VERILOG HDL语言的精简培训教程，是值得一看的好东东！-IT IS VERY GOOD FOR BEGINNING
PS2_keyboard
- implement a PS/2 keyboard host controller by using verilog HDL.
moore
- moore状态机实验verilog代码，我已经调试好。希望供大家学习使用。-moore state machine code of verilog HDL.Debug it right.
music
- verilog HDL编写的文件，实现音乐播放，FPGA为EP2C8Q208C8N，编译通过，详细内容参考代码。-verilog HDL documents prepared, the music player, FPGA to EP2C8Q208C8N, compile, details reference code.
ade
- 用VERILOG HDL 语言实现一个8位串行乘法器-VERILOG HDL language with an 8-bit serial multiplier
mult_addtree
- 用VERILOG HDL 语言实现一个4位的流水线乘法器-VERILOG HDL language with a 4-bit pipelined multiplier
9054verilog
- 9054时序控制 Verilog HDL-9054 Verilog HDL timing control
hdl
- ACTEL串口收发 Verilog语言描述-ACTEL serial port transceiver
hdl
- ACTEL FPGA 1602显示，verilog描述-ACTEL FPGA 1602 show, verilog descr iption
hdl
- ACTEL FPGA 交通灯，Verilog描述-ACTEL FPGA traffic lights, Verilog descr iption
MCU_V_PWM_16bit
- 单片机通过总线，将占空比和频率送到CPLD/FPGA中，并控制PWM输出.采用Verilog HDL语言编写。-Microcontroller by bus, the duty cycle and frequency sent to the CPLD/FPGA in, and control the PWM output. Using Verilog HDL language.
CMI_endecod
- Verilog HDL实现CMI编码和解码，在QuartusII下完成仿真验证。-CMI encoder an decoder using Verilog HDL.
music
- 用FPGA实现的歌曲“梁祝”播放程序，用Verilog HDL编写-FPGA implementation with the song " Butterfly Lovers" player, written with Verilog HDL
viterbi
- This a code generator for some kinds of viterbi decoders. It can generate the synthesiable verilog HDL codes. These have been verified under simulation. The generator itself is released under GPL license but the Verilog HDL codes generated by it is w
altpcie_64b_x8_pipen1b
- PCIE的软核程序，基于Verilog HDL语言，应用于FPGA的高级编程应用中。-PCIE soft nuclear program, based on Verilog HDL language, used in high-level FPGA programming applications.
VerilogHDLxiayuwen
- Verilog HDL数字设计与综合 夏宇闻译（第二版）-Digital design and synthesis of Verilog HDL translation of Xia Yu Wen (Second Edition)
verilog
- 各种基础的Verilog hdl实验的实验报告，包括D触发器，移位寄存器，选择器，译码器等等，有很详细的操作步骤，对于初学者很有用。-All based on Verilog hdl experiments are reported, including the D flip-flops, shift registers, selectors, decoders, etc., there are detailed steps, useful for beginners.