搜索资源列表
hdl-2015_r2
- AD9361 IP核,Windows版本,Vivado2015.2(AD9361 IP core, used on Windows, Vivado2015.2)
hdl-2016_r2.tar
- AD9361 IP核,Linux版本,Vivado2016.2(AD9361 IP core, used on Linux, Vivado2015.2)
hdl-2016_r2
- AD9361 IP核,Windows版本,Vivado2016.2(AD9361 IP core, used on Windows, Vivado2016.2)
spram
- verilog编写的spram,包含顶层模块,控制模块和spram本体,其中spram为Altera提供的ip核,已在quartus 16上运行通过(Verilog written in spram, including the top-level module, control module and spram ontology, where spram is the IP kernel provided by Altera, has been running on quartus 16)
FFT v1
- IP core fft verilog code example
06_pll_test
- 锁相环IP核的使用,包括详细的配置,适合学习使用;(The use of PLL IP core, including detailed configuration, suitable for learning to use;)
10_rom_test
- rom ip核的配置,以及测试文件,适合初学者使用。(ROM IP core configuration, as well as test files, suitable for beginners to use.)
parallel_norflash_test
- ISE工程,并行nor flash的读、写、擦出,其中有个调用FIFO16-16的IP核,已经在工程中(ISE engineering, parallel nor FLASH read, write, erase, where there is a call FIFO16-16 IP core, has been in the project)
AMBA_VIP
- AMBA 总线IP 核Verilog代码(AMBA bus IP Verilog code)
Module基础全集
- 如题,各种veirlog 基础代码大全,虽功能不及ip核,但却可以学习到很多(For example, all kinds of veirlog base code, though not as functional as IP core, can learn a lot)
rtl
- 基于S10新品的2x2矩阵乘模块,附带双精度的乘法,除法ip核(2x2 matrix multiplication module based on S10 new product, with double precision multiplication, division IP kernel)
14_ethernet
- 使用verilog语言实现了udp发送 接收(Implementation of UDP sending and receiving)
iir_2n_ip_float_demo
- 使用altera提供的ip核,实现了浮点数运算的2阶iir滤波器,结果与matlab运算结果相同。(Using the IP core provided by Altera, the 2 order IIR filter of floating point operation is implemented, and the result is the same as that of MATLAB operation.)
at7_ex04
- 通过LED闪烁控制器的代码,使用Vivado工具配置定义一个IP核,在用户工程中可随意添加这个IP核作为设计的一部分,如同Vivado自带的IP核一样方便调用和集成。(Through the code of the LED scintillation controller, the Vivado tool is configured to define a IP core, and the IP kernel can be added as part of the design at rando
FIR设计实现sgh
- FIR滤波FPGA实现 ,已在仿真软件上验证实现,不是IP核,不是ip核。(FIR filter FPGA implementation, has been verified in the simulation software, not IP core, not IP core.)
PLL
- 本次的设计主要任务是学会调用锁相环 IP 核,并对其进行仿真, 具体要求如下:(1)熟练掌握调用锁相环 IP 核的详细步骤。将 50M 的时钟分成 20MHz 和 100MHz 两个时钟(2)对锁相环进行仿真,验证 调用的锁相环的正确性。(The main task of this design is to learn to call the phase-locked loop IP core.)
tcp_ip_core_w_dhcp_latest.tar
- 以太网协议 TCP/IP/DHCP协议verilog实现(Ethernet IP/TCP/DHCP verilog source code)
sobel
- 由Verilog编写在FPGA实现sobel算法应用于图像边缘检测,工程文件可在quartus13.1以上版本打开;工程使用到ram、fifo、pll三种ip核,design文件夹下包含ram、fifo、vga控制以及串口收发和sobel算法模块,sim和doc文件夹下分别包含modelsim的仿真模块和仿真结果;测试时将200*200分辨率的图片用matlab文件夹下的matlab脚本压缩、二值化,再将生成文件中数据用串口发给FPGA,边缘检测结果会通过VGA输出。(Written by Ve
USB2.0的IP核(详细verilog源码和文档)
- USB2.0的IP核(详细verilog源码和文档).rar
ethernet_ip_verilog
- 以太网的ip,用verilog写的,包含testbench,用于FPGA以太网设计参考