搜索资源列表
MultifunctionDigitalClock
- quartus软件环境下采用verilog语言编写的多功能数字钟-quartus software environment using verilog language multifunction digital clock
p_s
- 用Verilog HDL语言进行串并转换，并通过Quartus Ⅱ 功能仿真验证-Series with the Verilog HDL language and converted, and through functional simulation Quartus Ⅱ
s_p
- 用Verilog HDL语言进行并串转换，并通过Quartus Ⅱ 功能仿真验证-With the Verilog HDL language and string conversion functions through simulation Quartus Ⅱ
kbmjsq
- 用Verilog HDL语言实现可变模计数器的功能，并通过Quartus Ⅱ 功能仿真验证-Variable with the Verilog HDL language to counter the function module and function through simulation Quartus Ⅱ
zmstz
- 用Verilog HDL语言实现正码速调整的功能，并通过Quartus Ⅱ 功能仿真验证-Verilog HDL language used is code rate adjustment function, and functional simulation by Quartus Ⅱ
071221088
- 实现一个简单的单周期流水线CPU，使用verilog语言开发 在quartus平台下运行-Implement a simple single-cycle pipelined CPU, using verilog language development platform running in quartus
061110061
- 在quartus平台下使用verilog语言编程实现简单的单流水线CPU，可以执行16条基本指令-Quartus platform in the verilog language programming using a simple single-line CPU, can perform 16 basic instructions
firfilter14
- 用Quartus II实现综合布线，要求充分利用Altera Stratix/Stratix II的器件的DSPBLOCK资源，Quartus II综合出的系统最高工作频率达到270Mhz以上.用Verilog进行编程。-Pipeline FIR structure。
SDRAMtest
- 使用quartus软件打开 内含sdram测试文件代码语言为verilog 备注清晰，适合初学者-Quartus software using open source test file containing sdram verilog Remarks clear language, suitable for beginners
Verilogexamples
- Verilog初学编程实例，包括源程序及QuartusⅡ仿真结果，适合初学者了解学习-Verilog beginner programming examples, including source code and Quartus Ⅱ simulation results, suitable for beginners to understand the learning
quartus_ii_tutorial_hierarchical
- quartus guide book for verilog
lcd
- 用Verilog写的数码管动态显示代码，可以直接使用，在quartus ii软件9.0以上版本运行-Verilog digital control with dynamic display of written code, can be used directly in the quartus ii software, version 9.0 or above to run
ex9
- 一个I2C通信协议的verilog代码，开发环境是Quartus 2,产生结果在数码管上显示-I2C communication protocol of a verilog code, development environment is Quartus 2, produce the results shown in the digital control
61EDA_C2111
- 数字下变频设计。 在ALTERA的QUARTUS ii下实现。实用，好用。--Verilog language implementation of the digital do
or1200_wb_ram_gpio_pll
- Quartus ii项目，硬件平台为SOPC2000，能实现LED的各种显示控制及按键输入。包括硬件实现的Verilog及软件实现的C实现。SOPC系统的设计在Windows的quaruts ii 8.0上实现，软件部分在Ubuntu上实现。-Quartus ii project, the hardware platform for SOPC2000, to achieve a variety of LED display control and key input. Including Ver
miaobiao
- 秒表 数码管显示 采用verilog语言编写 Quartus II 9.0sp2 编译成功后生成的所有文件已包含-Digital display with stopwatch verilog language Quartus II 9.0sp2 successfully compiled all the files have been generated that contains
fft_256
- 256点的fft，使用verilog硬件描述语言实现，可以在quartus等仿真软件仿真-failed to translate
crc16_finished
- 使用Quartus II软件开发，编程语言为Verilog，实现的是FPGA源代码-Using the Quartus II software development, programming languages Verilog, FPGA source code to achieve the
FPGA
- 本文采用FPGA来模拟实际的乒乓球游戏。本设计是基于Altera 公司的FPGA Cyclone II 芯片EP2C35 的基础上实现，运用Verilog HDL 语言编程，Quartus II 软件上进行编译、仿真，最终在Altera 公司的DE2 开发板上成功实现下载和调试-In this paper, FPGA to simulate the actual tennis game. The design is based on Altera' s FPGA Cyclone II EP
QuartusII_shuoming
- QuartusII简易操作说明 VHDL 仿真器 利用Quartus II 产生.VHO 和.SDO利用在sim_lib 目录中的APEX20K_ATOMs.VHD 和 APEX20K_COMPONENTS.VHD 文件 Verilog 仿真器 -QuartusII VHDL simulator simple instructions generated by Quartus II. VHO and. SDO use in sim_lib directory APEX20K_