搜索资源列表
tut_quartus_intro_verilog
- 为Quartus II和DE2新手准备的tutorial，Verilog版本.-Verilog edition tutorial for beginners
DDR_CTRL
- DDR Verilog 控制器，quartus 10.1工程。适用Altera Cyclone® III starter board-DDR control quatrus 10.1，Altera Cyclone® III starter board
ex16_sd_vga_photo
- 基于Verilog语言的fpga VGA视频接口通讯的源程序，经验证可用，开发环境Quartus -Verilog fpga VGA port Quartus ii
CPLD-down2
- EPM240 Program,Quartus II 10.0,Verilog
lab13
- Quartus实现单周期处理器，利用verilog语言-verilog cpu design
MEMCTRL
- 基于verilog的存储控制器芯片设计的工程。使用 Quartus II 4.0 以上版本打开设计工程文件。-Based on the works of the the verilog storage controller chip design. Use the Quartus II 4.0 or later to open the design engineering documents.
m_sequence
- 用verilog语言描述了M序列（伪随机通信）的编码、解码、纠错等功能，本人通过了Quartus II 以及Modelsim的仿真。-Verilog language descr iption of the M sequence (pseudo-random communication) encoding, decoding, error correction, I passed the Quartus II and Modelsim simulation.
digital
- 原创-verilog数字钟-基于quartus-显示时分秒-整点报时-设置时段不报时-欢迎下载-Original-Verilog digital clock-based on quartus- Displays minutes and seconds- the whole point of time- set time period does not chime- Welcome to download
uartfifo
- uart 通用异步收发器 verilog 代码，实现自收发功能，quartus运行有效。-uart universal asynchronous transceiver verilog code, since the transceiver function, quartus operating effectively.
verilog_sw_led
- 采用verilog编写的FPGA程序，程序的功能是按键按键消抖，quartus II 开发。芯片型号是EP2C35F484C7，时钟50MHz。-FPGA verilog to write the program, the program function is the key button is debounced, quartus II development. The chip model is EP2C35F484C7, clock 50MHz
qpsk_prj
- 用verilog语言实现了qpsk选相方法的实现，quartus仿真通过，管脚映射后可用~-fullfill qpsk in verilog .you can use it directly in your project or you can simulate it again
iic
- 使用verilog编写的IIC程序，在Quartus中调试通过，初学者可以参考。-Verilog prepared IIC program in Quartus through debugging, and beginners can refer to.
counter10000
- verilog编写的10000计数器，完整的Quartus II project，仿真通过-counter10000，verilog，project，simulation past
IR
- FPGA实现的红外IR解码程序，已成功通过Quartus编译，可实现红外正确接收和数据解码提取。-This is a verilog IR decoding program. It has been already compiler through the QuartusII.
DE0_exercise
- Altera公司生产的DE2开发板上附带资料的10个实验代码，在Quartus II环境下开发，绝对有价值（部分是在DE0上实现）-experiments of DE2 ,Altera,developmented with verilog
dds
- 使用AD5559,结合quartus中的硬件描述语言,实现了雷达发射信号二相码信号-using AD9959 and combining with verilog to output a rada signal of Binary code
sdram_mdl
- verilog实现SDRAM控制器，quartus工程-verilog SDRAM controller, quartus project
11111
- 1、用FPGA/CPLD实现HS162字符液晶显示。 2、分析相应的功能要求，分析CPLD与字符液晶HS162的接口典型电路。 3、利用状态机的设计方法，通过指令编程实现对HS162-4液晶模块的读/写操作，以及屏幕和光标的操作。 4、编写模块的Verilog HDL语言的设计程序。 5、在Quartus II软件或其他EDA软件上完成设计和仿真。 -This design of a CPLD-based controls HS162 to achieve character
altera_sdram
- 基于quartus平台的sdram控制器设计（verilog 源码）-Based on the the quartus platform, the SDRAM controller design (Verilog source code)
counter
- 在Quartus环境下verilog语言编写的一个4位加数器，选择的是一位位进位，是学习时序的好例子-Quartus environment verilog language of a four addend, the choice is a binary, is a good example to learn the timing