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fenping16
- 十六分频verilog代码，经过quartus验证-16 divided verilog code verification after quartus
freq
- 等精度频率计的verilog实现，经过quartus编译-Verilog to achieve equal precision frequency meter
ifir_64
- verilog hdl, quartus.64阶的简单回声抵消器，采用的是基本的LMS算法，简单改进，可用于初期了解。功能背景是对通信领域中，比如打电话时自己的声音到达对方经对方环境多径反射又传回自己这边，即回声。为将回声消除采用回声抵消装置。-64 steps a simple echo canceller is used in the basic LMS algorithm, a simple improvement, can be used for the initial understa
smg
- 对某一引脚高电平计时并用三位数码管显示程序，每秒钟更新一次，quartus ii开发环境，verilog语言编程-Timing in response to a pin of the high level duration with three digital tube display .Quartus_II software development environment and Verilog language preparation
reg_32bit
- quartus 2中使用verilog编写32位寄存器-32-bit register
SAR_Send
- 对altera的RS编解码IP核进行仿真，并且写了编解码的控制模块，用verilog实现，通过仿真，编码和解码功能正确。-test of RS code and RS decode,by using quartus ii9.0 with the IP core
Code_NCO.zip
- 码数控振荡器相位累加器的位数N为32,利用verilog HDL语言在Quartus II 9.1中具体实现了载波和码NCO的设计。,The code numerically controlled oscillator phase accumulator bits N 32 verilog HDL language in the concrete realization of the design of the carrier and code NCO Quartus II 9.1.
Key_Xiaodou_Delay
- Verilog语言，Quartus II开发环境，按键延时消抖IP。-Verilog language, Quartus II development environment, key delay shake away IP.
verilog_anjianxiaodou
- quartus II下FPGA的基于verilog的按键消抖程序设计-Based verilog the key debounce procedures of design
dab1814114c3
- 此為採用ALTERA所做的DDR 控制器(verilog)- File/Directory Descr iption ============================================================================= \doc DDR SDRAM reference design documentation \model Contains the verilog SDRAM model \route
fdivision
- 一个分频的quartus工程，用verilog写的，改变i的值可以实现任意分频，绝对原创-Quartus project a divide verilog write, change the value of i can achieve arbitrary divide absolute originality! ! !
Quartus_II-training-file
- Quartus 培训和使用教程，包括使用原理图输入，使用Verilog建立工程等-Quartus training file，include usingthe schametic to create project,and use the verilog file to create the project.
traffic
- 用Quartus开发使用verilog语言编写的数字交通灯控制程序-Quartus development using Verilog language digital traffic lights control procedures
LAB-1
- 用组合电路实现的ROM,编程环境为QUARTUS II，verilog编写的例程。-The combinational circuit ROM programming environment QUARTUS II, verilog written routines.
1
- 2选1 Verilog 语言的编程 环境是Quartus II 6.0 -2 choose 1 Verilog language programming environment is Quartus II 6
EXP6
- 基于Verilog 的实现秒表的程序 先要安装Quartus II 6.0 可用看到时序仿真-To achieve a stopwatch program Verilog to install Quartus II 6 can be used to see the timing simulation based on
my_test_rw_pack9
- 基于Verilog HDL的SDRAM控制器。 实验条件： 工具：Quartus II 6.0 ,SignalTap II FPGA：Altera Cyclone EP1C12Q240C8N SDRAM：HY57V283220T-6-SDRAM controller based on Verilog HDL. Experimental conditions: Tools: Quartus II 6.0, SignalTap II FPGA: Altera Cyclon
key
- Verilog初学者实验程序。已在quartus下测试成功。-Verilog beginners experimental procedures. Been in quartus under test success.
lcd
- Verilog初学者实验程序。已在quartus下测试成功。-Verilog beginners experimental procedures. Been in quartus under test success.
parall_ad_da
- Verilog初学者实验程序。已在quartus下测试成功。-Verilog beginners experimental procedures. Been in quartus under test success.