搜索资源列表
Verilog
- 用verilog实现的电子日历程序,在Quartus II上编译通过-Implemented using verilog electronic calendar program, compiled by the Quartus II
fft
- Quartusii的FFT,使用Verilog HDL 语言的FFT-FFT based on Quartusii
cordic
- 在QUARTUS环境下，通过Verilog实现cordic，产生sin，cos-In QUARTUS environment, through the Verilog implementation cordic, generate sin, cos
LCD12864
- LCD12864显示 verilog hdl编译已通过 编译器 Quartus II 9.0sp2 所有文件已包含-LCD12864 Show verilog hdl compiler has compiler Quartus II 9.0sp2 through all the files included
SRAM
- 语言：VHDL 功能：利用VHDL编程，实现FPGA对SRAMIS61LV24516的读写操作。由于是针对IS61LV24516型号进行读写的，如果不是此型号的SRAM需要对程序进行时序修改。 仿真工具：modelsim 综合工具：quartus -Language: VHDL function: the use of VHDL programming, FPGA on SRAMIS61LV24516 read and write operations. Because it
bch_encode
- this bch encoder verilog code-this is bch encoder verilog code
CPU
- 一个完整的流水CPU设计，quartus平台，Verilog实现-CPU design a complete water, quartus platform, Verilog realization
i2c
- I2C IP CORE Verilog quartus-I2C IP CORE Verilog quartusii
uart
- uart IP CORE Verilog quartus-uart IP CORE Verilog quartusii
my_kmp_matching
- KMP算法的Verilog HDL实现，模式串从模块的外部输入，计算next函数，然后进行KMP匹配。有仿真。环境为Quartus II 8.0 Web Edition。-Verilog HDL implementation KMP algorithm, pattern string from the module' s external input, calculate next function, then KMP matching. A simulation. Environment
serial_adder
- This is a simple Serial Adder for Quartus II. The source code is in verilog HDL
lift_control
- 利用Verilog设计的电梯控制器代码，通过QUARTUS进行仿真-Elevator controller design using Verilog， simulation by QUARTUS
cpu
- 一个简单的CPU设计，支持add，sub，mvi，mv四条指令，用Verilog语言编写，在Quratus II上编译通过，仿真正确。-A simple CPU design, support add, sub, mvi, mv four instructions, with the Verilog language, compiled by the Quratus II, the simulation is correct.
sci_to_mcbsp
- 自己写的 mcbsp 转 sci 和 sci转mcbsp 的verilog的程序，欢迎大家 指点，开发环境是Quartus II。-Write their own sci and sci mcbsp turn mcbsp turn the verilog program, we welcome the guidance, the development environment is the Quartus II.
ram
- verilog 编写的ram代码，开发环境为quartus-ram write verilog code development environment for quartus
SRAM
- Verilog 语言描述，SRAM的实验操作，Quartus中编译通过-Verilog language descr iption, SRAM experimental operation, Quartus compiled by
BPSK
- 用于BPSK调制的自行设计，说明如下： 1.matlab.txt中的程序是matlab平台下的.mat格式。目的是输出一个64*4的矩阵，矩阵的每个元素都为0~255间的整数。矩阵每行的四个数是一个码元的四个抽样点的量化值。但由于当前码元通过升余弦滤波系统时，受到前后共6个码元的共同影响，所以是由6个码元共同决定。这6个码元是随机的，可能是0也可能是1（双极性时可能是-1也可能是+1），故6个码元共2^6=64种情况，所以产生的矩阵是64*4。最后逐行输出这256个数。 2.
veolig_LCD12864
- Verilog语言驱动12864，显示英文。在Quartus II软件下编译通过-12864 Verilog language-driven show in English. Compiled in the Quartus II software through
Verilog
- 基于Quartus II 9.0 (32-Bit)的Verilog语言时钟程序，五个独立按键分别可调十分秒的加减和确定，此程序通过硬件调试成功。-Based on Quartus II 9.0 (32-Bit) of the Verilog language, clock, five independent second key addition and subtraction, respectively, is adjustable and determined the success of
Quartus-II
- Quartus II 使用方法,叫你如何使用Quartus创建verilog hdl文件，很好很强大-Quartus II, that you use methods how to use Quartus create verilog HDL files, was very, very powerful