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CummingsSNUG2002SJ_FIFO1
- Simulation and Synthesis Techniques for Asynchronous FIFO Design
documentsoffifo
- 介绍FIFO的文章，关于同步FIFO或者异步FIFO-FIFO introduced an article on synchronous or asynchronous FIFO FIFO
c22_FIFO.rar
- 精通verilog HDL语言编程源码之8——异步FIFO设计,Proficient in language programming verilog HDL source of 8- Asynchronous FIFO Design
yibu_FIFO_design
- 异步FIFO实例，精通verilog hdl中的例子，供大家学习-Asynchronous FIFO instance, in the example verilog hdl proficiency for all learning
ad_da_ctr
- 基于FPGA的ad和da转换Verilog代码，FPGA采用ep2c5芯片，做成异步fifo，ad芯片采用TI的ths1230,da芯片采用TI的TLV5619，仿真结果基本正确。-FPGA-based ad and da conversion Verilog code, FPGA using ep2c5 chip, made ??of asynchronous fifo, ad-chip using TI s ths1230, da chip uses TI s TLV5619, simula
sdh
- SDH是现代光纤通信中广泛应用的数据传输格式,在SDH帧结构中，前9列为开销字节，它包含了很多重要的信息，本程序为SDH开销的接收处理，查找帧头，分频，勤务话字节E1异步fifo。可拆为三段源代码，不知道能不能抵三个程序-SDH is a modern optical fiber communication is widely used in data transmission format, in the SDH frame structure, as the former 9 overhea
ASYNCFIFOXPXMOD
- 任意时钟配比的异步fifo.含有synplify ip库中的双端口ram。用于处理多时钟域问题。-Arbitrary ratio of asynchronous clock fifo. Containing synplify ip library of dual-port ram. Used to deal with the issue of multi-clock domain.
ps
- RS(204,188)译码器的设计 异步FIFO设计 伪随即序列应用设计 CORDIC数字计算机的设计 CIC的设计 除法器的设计 加罗华域的乘法器设计-RS (204188) decoder design of asynchronous FIFO design application design sequence was pseudo-CORDIC design of digital computer design CIC divider design Le Hua
ascfifotestbench
- 自写异步 fifo TESTBench 该fifo对初学者很有帮助！-Since the write fifo TESTBench asynchronous fifo very helpful for beginners!
0917afifo_s
- 采用同步异步信号的方式，将两个CLK统一到同一个时钟下工作，用同步FIFO实现异步FIFO-Asynchronous signals using synchronous way, two a clock CLK to the same uniform to work, using synchronous FIFO Asynchronous FIFO
Asynchronous_Resets_FILO
- 外国编程高手关于异步fifo和复位电路的精度论述。-Master a foreign programming asynchronous fifo and the reset circuit on the accuracy of exposition.
asyn_FIFO
- 该文档是学习异步FIFO 的参考文档，有需要的可以参考一下。-This document is an asynchronous FIFO to study the reference documents, there is a need that can be reference.
yfifo
- 一个异步FIFO，自己写的。初学多交流学习进步快！-An asynchronous FIFO, write your own. Beginners to learn and exchange more rapid progress!
fifo2
- 异步双时钟fifo，vhdl源代码。基本组成是定制的fifo加上空满判断逻辑，基本功能都有-Asynchronous dual clock fifo, vhdl source code. Fifo basic component is a custom air filled with the logic to judge the basic functions are
synchronousfifo
- 采用SystemC语言编写的异步FIFO,非常适合初学SystemC语言的人作为例子练习。-SystemC language using asynchronous FIFO, SystemC is suitable for beginners to practice the language of the people as an example.
asy_FIFO
- 用Verilog实现FIFO的异步设计，里面有详细的代码和各个模块的代码，经过调试可以使用-asynchronous FIFO design
javacalc
- 3.设计一个数据宽度8bit，深度是16的异步FIFO（读写时钟不相同）， 当读写时钟的频率分别为wrclk＝40MHz、rdclk＝20MHz时，仿真其逻辑波形。25,50 当读时钟比写时钟快时（wrclk＝20MHz，rdclk＝40MHz）， 如何保证读出的数据是写进去的有效数据？仿真验证你的设计。 对比第3题的同步FIFO，分析同步FIFO和异步FIFO的不同特性。-3. To design a data width of 8bit, depth is 16 as
SC16C752B
- The SC16C752B is a dual Universal Asynchronous Receiver/Transmitter (UART) with 64-byte FIFOs, automatic hardware/software flow control, and data rates up to 5 Mbit/s (3.3 V and 5 V). The SC16C752B offers enhanced features. It has a Transmission
sync_fifo
- 这个实现了一个异步的fifo ,通过同步的方法把异步fifo变为同步的fifo来实现，简化了硬件实现的工程-This implements an asynchronous fifo, by synchronizing the asynchronous method into a synchronous fifo fifo to achieve, simplifying the hardware implementation of the project
sdfsdFifo
- 这是一个异步fifo的Verilog 代码，该代码的功能是实现异步的first in first out-This is an asynchronous fifo in the Verilog code, the code' s function is to achieve asynchronous first in first out