搜索资源列表
AXI_MIG
- ISE生成的AXI接口的MIG，内存控制器，语言：verilog-ISE generated the AXI interface MIG, memory controller, language: verilog
eetop[1].cn_axibusregslice
- axi总线读写通道插入一级寄存器模块verilog源码,已验证- a slave interface is simple to achieve, need to look at
axi_slave_latest.tar
- AXI is AMBA4 compliant. code this code is a verilog imp lementation of AXI slae
demo_axi3_memory
- axi, ahp, app, verilog, integarader
src
- AXI Slave codes in verilog. Downloded from www.opencores.org free download
std_ovl_v2p7_Feb2013
- 目前最新的OVL库，里面是标准的ASSERTION模块，支持VHDL刚Verilog，最近在做AXI协议验证的时候用到，分享下-The latest OVL(open verification library),including all standard module of assertions(VHDL and Verilog). It can be used into AXI Protocl Verification. Just share with you guys.
axi_slave
- AMBA axi利用verilog搭建的axi_slave模块-AMBA axi use verilog module built axi_slave
axis_fifo
- VIVADO下使用verilog编码的axi fifo的简单使用，仿真通过，供初学者学习。-Use the following VIVADO verilog coding axi fifo simple to use, through simulation, for beginners to learn.
ddr_top
- verilog语言ddr3读写程序，axi总线协议，用于ddr3读写测试-ddr3 read and write
axi_jesd204b
- ADI JESD204接口的ADC与Xilinx FPGA接口IP，包含Verilog和VHDL源代码，AXI总线接口，ADC串行控制接口-ADI IP for interfacing JESD204 ADC to Xilinx FPGA, include Verilog/VHDL source code, AXI interface and serial config interface
uvm_axi-master
- axi uvm vip, verification model -axi system verilog