搜索资源列表
ps2
- ps2接口的实验程序，包含4个文件，其中有分频器-ps2 interface experimental procedures, including the four documents, including divider
freqdiv_simple
- frequency divider using VHDL quite simple expecially for beginners cheers
frediv
- 1:1占空比的分频器的VHDL实现，包括奇数和偶数分频。-1:1 duty cycle of the divider of the VHDL implementation, including the odd and even frequency.
dividerverilogdesign
- verilog 分频器设计 偶数分频器和奇数分频器-divider verilog design even and odd divider divider
buzzer
- 向蜂鸣器发送一定频率的方波可以使蜂鸣器发出相应的音调，该实验通过设计一个状态机和分频 器使蜂鸣器发出"多来咪发梭拉西多"的音调。-A certain frequency to the buzzer to send a square wave can make the appropriate tone buzzer, the experiment by designing a state machine and the divider to make the buzzer " made
fd
- 分频器（奇，偶，数分频）通过或的方法实现奇数分频，-frequency divider
fenpin
- 分频模块，实验板上的时钟频率太快，可以用分频模块来减小频率-Frequency modules, test board clock frequency too fast, the module can be used to reduce the frequency divider
50MSeparatefrequencydevice
- vhdl语言设计中常用到的50M分频器，可以以此设计出各种需要的分频器。-vhdl language commonly used in design to the 50M divider, can also be used to design the divider needs.
zzchufaqi
- vhdl 除法器 eda课程设计用。 设计一个两个五位数相除的整数除法器。用发光二极管显示输入数值，用7段显示器显示结果十进制结果。除数和被除数分两次输入，在输入除数和被除数时，要求显示十进制输入数据。采用分时显示方式进行，可参见计算器的显示功能。-divider vhdl eda curriculum design purposes. Design a two five-digit integer divider division. Enter the value with the lig
freq_divider
- 一个时钟分频器，可以实现任意整数倍或者分数倍的分频功能。-A clock divider can be an arbitrary integer multiple or fraction of times the frequency function.
div8M_v
- 基本的分频器，用于将时钟频率降低一半。包含两个接口，只使用寄存器，未使用线网类型。-The basic divider for halving the clock frequency. Contains two interfaces, using only regs instead of wires.
ISE_lab16
- 使用VHDL语言设计数字钟。 数字钟由晶振、分频器、计时器、译码器、显示器等组成-Digital clock design using the VHDL language. Digital clock from the crystal oscillator, frequency divider, timer, decoder, display and other components
div_5
- 一种技术分频器的设计，5分频为例，Verilog源码-A technology Divider, 5-band case, Verilog source code
verilog
- Verilog HDL 1.红外线发射调制电路 2.分数分频 3.最大公约数和最小公倍数 4.秒表-1.infra transmission modulator 2.fractal frequency divider 3.maximal common divisor 4.timer
hightfrquencydivider
- 用VerilogHDL语言实现一个被除数为8位，除数为4为的高效除法器，实现高效的除法功能-VerilogHDL language with a dividend of 8 bits, the divisor is 4 for the high divider, a high efficiency of the division function
11
- 本题为verilog HDL实现的占空比为1：1的分频器-Divider
shiyanbaogao
- 了解ISE平台的基本环境，编译程序，在MC8051 IP核中，要求实现：增加PLL锁相环，扩大内部RAM，定时器，串口和外部中断等资源，并增加乘法器和除法器的功能。-ISE platform to understand the basic environment, compiler, the MC8051 IP core, the requirement to achieve: increased PLL phase-locked loop, expanding the internal RAM
BCD_COUNTER
- Binary Counting A binary counter can be constructed from J-K flip-flops by taking the output of one cell to the clock input of the next. The J and K inputs of each flip-flop are set to 1 to produce a toggle at each cycle of the clock input. For eac
clock_divider.vhd
- A generic clock divider described in VHDL language
deccount16nr
- 16位任意计数分频器,VHDL语言实现,通过测试-Any count 16-bit divider, VHDL language