搜索资源列表
fenpinqi
- 分频器部分 参考这个是对的 但是请与自己的程序相匹配-Part reference divider, but this is the right procedure for you and your match
fenpinqi
- 基于VHDL 语言的分频器设计， EDA； CPLD； VHDL； 仿真-Divider based on VHDL language design, EDA CPLD VHDL Simulation
61EDA_D807
- VHDL数频分频器设计 整数，奇数，偶数，半数等的分频 -VHDL design of an integer number of frequency divider, odd, even, half of the frequency, etc.
verilog_n_evendivider
- verilog 中很好的n倍奇数分频器，开发环境为ISE10.1，仿真环境为modesim6.3-n times in good verilog odd divider, the development environment for ISE10.1, simulation environment for the modesim6.3
adc
- 掌握S3C2410A的模/数(A/D)转换器的应用设置，进行电压信号的测量.使用AIN0和AIN1测量两路直流电压，并将测量结果通过UART0向PC机发送.-NC divider based on VHDL language, the designer can modify the frequency coefficient code
c
- 除法器 课程设计 汇编语言 不恢复余数法-Divider assembly language course design
fenpin
- 7分频器 是指将不同频段的声音信号区分开来，分别给于放大，然后送到相应频段的扬声器中再进行重放。在高质量声音重放时，需要进行电子分频处理-seven frequency divider
Addr_Generator
- 其中start是开始信号，上升沿启动控制单元；CLK是工作时钟；CtrlAddr是读取控制字时的地址；CtrlData是读取的控制字；Reading是读信号；EOP是本次AD采样完成信号，只有当AD1和AD2均完成后EOP才为高；EN是允许信号，启动分频器、地址发生器；N是分频系数；Addr1和Addr2分别是AD1和AD2数据存储的起始地址；NUM1和NUM2分别是采样点数。 控制字分别表示分频系数为2，AD1起始地址为1，采样点数5，AD2起始地址为3，采样点数为4。 -Where
VHDL
- 分频器实现不仅可以以偶数倍分频，还可以以基数被分频，可以调整占空比-Divider to achieve not only the frequency can be even several times, but also can be divided base, you can adjust the duty cycle
clock
- 闹钟系统的控制 闹钟系统的移位寄存器 闹钟系统的闹钟寄存器和时间计数器 闹钟系统的显示驱动器 闹钟系统的分频器 闹钟系统的整体组装-Alarm system, alarm system control shift register alarm system alarm registers and the time counter display driver alarm system, alarm system, alarm system, the overall a
vhdlchufaqi
- 这是一个基于VHDL语言的bch除法器，其功能就是实现二进制除法，采用移位的方式进行-This is based on VHDL language bch divider, its function is to achieve binary division, the way by shift
ADC0832
- 本程序为数字电压表输入电压经89k电阻和10k精密电位器分压测试电压为0～51v，可用表校对。-This program is a digital voltmeter input voltage by the 89k and 10k resistor divider potentiometer precision test voltage is 0 ~ 51v, can form proofreading.
fenpin-FPGA
- 本文通过在QuartursⅡ开发平台下，一种能够实现等占空比、非等占空比整数分频及半整数分频的通用分频器的FPGA设计与实现，介绍了利用VHDL硬件描述语言输入方式，设计数字电路的过程。-In this paper, the development platform in Quarturs Ⅱ, one can achieve such duty, such as the duty cycle of non-integer frequency division and semi-integer
zq_100us
- 利用VHDL实现偶数分频，设计了一种能够实现等占空比的任意偶数分频、等占空比任意奇数分频、不等占空比的任意半整数分频的较为通用的分频器,并通过QuartusII进行了功能仿真。 -Use VHDL to achieve an even frequency, designed to achieve such a duty cycle of any even frequency, such as the duty cycle divide any odd number, ranging from
dvf
- 基于VHDL语言关于分频器进行基本设计，简单易懂-Divider based on VHDL, the basic design, easy to understand
chufaqi
- 除法器程序，采用Verilog语言编写，并在CPLD开发板上经过验证，正确无误，希望对大家有用-Divider procedure for the Verilog language, and CPLD development board verified and correct, we hope to be useful
cong-50Mfenpin500HZ
- 关于分频器的设计与仿真，从50M到500 hz，对于个人很有参考价值。-Design and simulation on the divider, from 50M to 500 hz, a good reference for the individual.
progrm
- FPGA二分频代码，可实现分频器的功能，用于频率的分频-FPGA binary frequency code, the function can be realized divider for frequency division
clk
- 二分之一分频器及其测试程序，是用modelsim仿真实现-One half of the divider and the test procedure is used modelsim Simulation
Verilog
- 一些关于Verilog分频器设计.doc-Verilog divider design. Doc