搜索资源列表
ram
- a 16 by 4 ram is used for many applications as a basic component such as fifo and stack etc
fifo_core
- 经典的FIFO实现源码，里面有三种类型，是xilinx工程师写的，经典-Classic source FIFO implementation, there are three types, are written by xilinx Engineer, classical
Flash_ROM_lab
- 用SmartGen生成一个256*8的大小同步FIFO，并通过串口发送数据初始化FIFO。然后，再通过串口返回到上位机的串口调试程序显示，确认数据是否正确。-SmartGen generated with a size of 256* 8 Synchronous FIFO, and sending data through the serial port to initialize FIFO. And then back through the serial port to the PC ser
usb
- USBHostSlave is a USB 1.1 host and Device IP core. – Supports full speed (12Mbps) and low speed (1.5Mbps) operation. – USB Device has four endpoints, each with their own independent FIFO. – Supports the four types of USB data transfer control,
camera_up
- Camera Interface模块是视频输入转换存储模块。该模块一端接通用的video camera设备，另一端接AHB总线。实现了将Camera捕捉到的数据进行转换、并通过DMA存储到memory中。该IP支持ITU-R BT 601/656 8-bit 模式。支持YCbCr, RGB格式输入。可以将camera产生的YCbCr信号转换成24bit RGB 信号，然后下采样生成16bit RGB 5：6：5的LCD能直接读取显示的数据。该设备支持图像的镜像和翻转，以便适应手持式设备在移动环境
gencontrol
- 高速任意波形产生器控制模块 控制NCO,FIFO，并串转换-hign-speed wfgenerator control
fifodd
- 一个深度为32，字长为8_bit FIFO（先进先出）寄存器，有寄存器空、寄存器满和寄存器溢出信号。-A depth of 32, word length for 8_bit FIFO (FIFO) register, a register space, register and register full signal overflow.
FIFO
- VHDL code for first in first out register
fifo1k_32
- PCI 数据采集控制卡的内部 FIFO处理代码-Data Acquisition and Control Card PCI internal FIFO handling code
fifi
- FIFO code written in VHDL
fifo_sync
- 用VHDL语言编写的FPGA程序,实现异步FIFO的功能。这个程序设计十分巧妙，精简。 -vhdl fifo sound code
THS1206
- FPGA来实现数据采集，AD采用TI公司的THS1206，高速并行AD，内含16字FIFO，降低硬件复杂度。-FPGA to realize data acquisition, AD using TI company s THS1206, high-speed parallel AD, containing the 16-character FIFO, to reduce hardware complexity.
fifo
- first in first out VHDL code
caiyang
- 种用FPGA 实现对高速A/ D 转换芯片的控制电路,系统以MAX125 为例,详细介绍了含有FIFO 存储器的A/ D 采样控制电路的设计方法,并给出了A/D 采样控制电路的V HDL 源程序和整个采样存储的顶层电路原理图.-Species with FPGA to achieve high-speed A/D conversion chip control circuit, the system as an example to MAX125 details FIFO memory cont
FIFORAM
- FIFO RAM 存储器以FIFO形式进行的读取-FIFO RAM
FIFO
- 一个先入先出FIFO的VHDL实现，程序经过了编译验证。-A FIFO FIFO to achieve the VHDL, verification procedures have been compiled.
yuyincaiji
- 语音采集与回放系统源代码：1.为了使读音数据存储的时间更长，速度更快，选用了256K*16Bit的SRAM；2.为了减少单片机的控制复杂度，使用了FPGA来控制SRAM的读写操作，节约了不少单片机的I/O资源；3.为了以后的高速数据存储，本设计中加入了fifo,其位宽及深度可在程序中自由设置，方便灵活。-Speech acquisition and playback system source code: 1. In order to make pronunciation longer data
spartan6_fpga_blockram_user_guide
- Spartan6 FPGA中的块存储器使用指南，可以构建为FIFO，ROM，RAM，移位寄存器等。-Spartan6 FPGA block memory in the User Guide, you can build for FIFO, ROM, RAM, shift registers and so on.
fifo2
- FPGA的异步先入先出程序，VHDL的fifo-VHDL and fifo