文件名称:camera_up
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- 上传时间：2012-11-16
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文件大小：32.24kb
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Camera Interface模块是视频输入转换存储模块。该模块一端接通用的video camera设备，另一端接AHB总线。实现了将Camera捕捉到的数据进行转换、并通过DMA存储到memory中。该IP支持ITU-R BT 601/656 8-bit 模式。支持YCbCr, RGB格式输入。可以将camera产生的YCbCr信号转换成24bit RGB 信号，然后下采样生成16bit RGB 5：6：5的LCD能直接读取显示的数据。该设备支持图像的镜像和翻转，以便适应手持式设备在移动环境中图像的捕捉。可变的同步信号极性使得可以兼容各种摄像头外设。Camera Interface兼容AMBA规范， AHB SLAVE接口，用于读取软件配置数据和设置数据存放地址和1帧数据占用的空间。-The Camera IP Core is small and flexible video data coverter. It is connected to a typical video camera ICs with 8-bit digital video data, Horizontal synchronization and Vertical synchronization signals. The core is connected through FIFO to a WISHBONE bus on the other side. Both sides of the core can operate at fully asynchronous clock frequencies. The Camera IP Core convertes 4:2:2 YCbCr video data (sometimes called YUV, but not totally the same Y is the same, while Cb and Cr are U and V multiplied by a constant) to a 24-bit RGB. 24-bit or 16-bit RGB data, downsampled from 24-bit RGB, is then sent to the system (video) memory, however conversion can also be by-passed. Interrupt can be generated after frame-buffer in system (video) memory is filled up or after setable number of horizontal lines written to frame-buffer.
相关搜索： 656
ip camera
WISHBONE
rgb
ahb
The Camera IP Core is small and flexible video da
ycbcr
wishbone bus
ip core
buffer in vhdl
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下载文件列表
wptr_full.v
cam_master_addr_gen.v
cam_master_fsm.v
camera_cb_calc.v
camera_cr_calc.v
camera_define.v
camera_fifo_ctrl.v
camera_master.v
camera_slave.v
camera_sp_conversion_calc.v
camera_sync_ctrl.v
camera_synchronizer_flop.v
camera_top.v
camera_y_calc.v
clock_divide.v
fifomem.v
format656to601.v
rptr_empty.v
sync_r2w.v
sync_w2r.v
cam_master_addr_gen.v
cam_master_fsm.v
camera_cb_calc.v
camera_cr_calc.v
camera_define.v
camera_fifo_ctrl.v
camera_master.v
camera_slave.v
camera_sp_conversion_calc.v
camera_sync_ctrl.v
camera_synchronizer_flop.v
camera_top.v
camera_y_calc.v
clock_divide.v
fifomem.v
format656to601.v
rptr_empty.v
sync_r2w.v
sync_w2r.v
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