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example
- 我FPGA开发板的程序!!!包括数、码管iic、VGA、乘法器、串口。加法器、比较器、状态机等等等了,主要是VHDL的也有部分好似Verilog的。参考下吧-verilog...vga..uart...add...etc..
uart_core(V2_0)
- 本例为自己编好的VHDL的基于uart的FPGA的 设计。-In this case for their own good VHDL code uart of FPGA-based design.
UARTVHDL
- VHDL语言写了uart接收单片机发送数据的程序,并用数码管显示96-VHDL uart fpga
uart_vhdl_verilog
- 串口FPGA的实现源码,VHDL和Verlog两种语言源代码。-UART FPGA implementation source code, VHDL and Verlog two languages source code .
Hex2Verilog
- 《基于VHDL的FPGA与NIOS II实例精炼》第十八章 UART核的应用 - 视... -《基于VHDL的FPGA与NIOS II实例精炼》第十八章 UART核的应用- 视...
topone
- 基于火龙刀开发板的FPGA和PC的UART串口通信的VHDL实现,支持LCD实现分页显示和LED 数码管显示。-FPGA and PC UART communication module implemented by VHDL, running on Dragon platform, with support of LCD and LED display.
UART_final
- 利用vhdl硬件描述语言,模拟异步通用串行接口UART的通信方式,已在fpga上实际测试,通信性能不错,有一定的参考学习价值!-Using vhdl hardware descr iption language, simulated UART asynchronous serial interface common means of communication, the actual test in fpga, communication performance is good, there i
FEP1C3_12_7_SP
- 基于FPGA的信号采集及频谱分析,用VHDL编写,压缩包里是Quartus下的工程。AD采样用状态机实现现,并存入LPM_RAM。设计了一个UART模块(也是状态机实现的),可将数据发到PC机上。 已通过测试。 -FPGA-based signal acquisition and spectrum analysis, using VHDL prepared compression bag Quartus engineering. AD sampling using the state mac
uart_rx
- 用VHDL语言实现的Uart串口通信程序。在xilinx公司FPGA芯片验证过。-Uart serial communication program using VHDL. Validation in xilinx Company FPGA chip.
UART_VHDLCodes
- 基于VHDL的异步串口收发器,在FPGA上设计Uart接收模块实现从pc接收串口数据; 在FPGA上设计Uart发送模块,把从pc接收的数据的16进制值加1再发送给PC; 设计单片机和FPGA接口模块,把接收到的数据送给单片机,并显示在LCD上 -VHDL-based asynchronous serial transceivers Uart receive module in the FPGA design from pc to receive serial data desig
uart_lcd
- 基于FPGA的UART通信,并用LCD(1602)显示通讯状态和通讯的数据。通过在ALTERA公司生产的DE2-115开发板上运行,证明此程序稳定可靠。时钟为50MHz,语言为VHDL,状态机。-FPGA-based UART communication, and LCD (1602) show the communication status and data communications. DE2-115 development board by ALTERA Company product
FPGA_UART
- FPGA实现UART串口通信协议 采用VHDL语言,顶层文件采用原理图的方式,简洁直观-FPGA Implementation of UART serial communication protocol
uart16750_latest.tar
- UART Module VHDL CODE TESTED ON FPGA
VHDLRS232Slave
- 本模块的功能是验证实现和PC机进行基本的串口通信的功能。需要在PC机上安装一个串口调试工具来验证程序的功能。程序实现了一个收发一帧10个bit(即无奇偶校验位)的串口控 //制器,10个bit是1位起始位,8个数据位,1个结束 //位。串口的波特律由程序中定义的div_par参数决定,更改该参数可以实 //现相应的波特率。程序当前设定的div_par 的值是0x145,对应的波特率是 //9600。用一个8倍波特率的时钟将发送或接受每一位bit的周期时间 //划分为8个时隙以
uart_serial_vhdl
- fpga例程:用实fpga现uart串口通讯的vhdl详细代码,附一个串口通讯助手小插件-fpga routines: solid fpga vhdl now uart serial communication code in detail, with a small plug-in serial communications assistant
uart_tx
- It is an UART interface that is written by me in VHDL to receive and send datas from/to FPGA.
M130095EC
- vhdl code for uart. data tx from pc to fpga nd vice versa
UART_FPGA
- 此vhdl程序实现了在FPGA上构建UART通信串口。分为两部分,UART的发送端transfer和接收端receiver。需要外部根据需求提供波特率时钟。-This program implements the building vhdl UART serial interface on the FPGA. Divided into two parts, UART transfer sender and receiver receiver. Required to provide the ba
uartfifo
- FPGA简单应用,VHDL程序,串口UART驱动程序,供学习参考。-FPGA and simple application, VHDL program, UART serial port driver, provide the reference for the study.
UART_TXD
- uart标准协议fpga代码,基于vhdl语言,实现uart协议发送功能-uart standard protocol fpga code, based on vhdl language, to achieve uart protocol transmission function