搜索资源列表
mysinrom
- 在ise中，使用IP内核建一个rom文件，通过寻址的方式输出数据。-Ise in IP cores built a rom file, output data by addressing the way.
MULTI4BIT
- 4位乘法器由于所使用的软件是ISE，没有LPM_ROM可以直接调用，所以此设计直接调用的乘法器的IP核来完成此功能，达到同样的效果。-Four multiplier
fir_compiler_ds534
- 详细的描述了XILINX ISE软件里的IP核的内部结构。详细的介绍了滤波器的各个内部机构和各个功能。-A detailed descr iption of the internal structure of the the XILINX ISE software IP core. Detailed introduction of various internal organs and the various functions of the filter.
fifo_ip
- 本程序是利用ise平台提供的IP核设计出的fifo，通过过上机运行检测。-This procedure is to use ise platform provides IP core design a fifo, passed through the machine running the test.
ram_ip
- 本程序是利用ise平台提供的IP核设计出的ram，已通过上机运行检测。-This procedure is to use ise platform provides IP core design of the ram, has passed the test on the machine running.
rom_ip
- 本程序是利用ise平台提供的IP核设计出的rom，通过上机运行检测。-This procedure is to use ise platform provides IP core design out rom, through testing on the machine running.
a
- 用verilog实现除法器，调用了ip核，不仅有源代码，还有测试程序的时序编写-verilog ise divider
296517dcm
- 基于ISE 12.4的IP 核调用 DCM 其功能是将开发板上的系统时钟变为任意的所需时钟 适合初学者学习-ISE 12.4 IP core based on DCM and its function is to call the board will develop into any desired system clock clock for beginners to learn
con_ram_success
- 利用ise中的ip核，实现在任意地址存储和读取数据-In the ise， using ip core, arbitrary address storing and reading data
rom123
- 利用ise中的ip核，实现rom的基本功能，通过此程序，学习掌握rom的工作原理及特性-In ise the， using ip core, implement basic functions of the rom and learning to master the working principle and characteristics of the rom
add_success
- 在ise中，实现两个ip核分别做加数和被加数，并将结果存在另一个ip-In ise, the realization of two summand and ip nuclear summand were done, and the results there is another ip
LEDs
- ISE实现流水灯，并使用开关控制流水灯走动速度，对于硬IP核初学者很有帮助，代码绝对在ISE14.6上做过验证。-ISE achieve water lights, and use the switch to control light water walking speed, hard IP core for beginners, code validation is absolutely done on ISE14.6.
CAN_IP_2014-4-20
- CAN IP核的详细实现 直接运用 可以用ISE直接打开-CAN IP USE
20140825
- FPGA设计在设计过程中使用ISE软件自带的IP核时，消耗资源太大的时候，需要自己编写滤波器的源代码，这里给出我们常用的串行FIR核的verilog语言代码设计文件，并通过作者时序仿真验证，并用于实际的项目中。-The FPGA design in the design process of ISE software used to own the IP core, consume resources is too big, need to write your own source code
FIR
- FPGA设计在设计过程中使用ISE软件自带的IP核时，消耗资源太大的时候，需要自己编写滤波器的源代码，这里给出我们常用的串行FIR核的verilog语言代码设计文件，并通过作者时序仿真验证，并用于实际的项目中。-The FPGA design in the design process of ISE software used to own the IP core, consume resources is too big, need to write your own source code
Xilinx_DDR2_IP_TEST
- 本文档对Xilinx 公司FPGA开发环境中ISE中如何调用DDR2 IP进行了详细的说明。直接例化IPCORE,采用无TESTBENCH，无PLL的方式.-This document FPGA from Xilinx ISE development environment how to call DDR2 IP for a detailed descr iption. Direct instantiation IPCORE, no-TESTBENCH, no PLL ways.
Xilinx_DDR
- 本文档对ISE开发环境利用MIG调用DDR2 IP CORE进行了进行了详细的介绍，对初学者很有帮助。其中FPGA芯片为Xilinx公司SP6 FPGA, DDR2 内存为Micron 公司的一款 R2 MT47H128M8 芯片。-This document calls ISE development environment using MIG DDR2 IP CORE conducted a detailed descr iption, very helpful for beginners.
complexMul
- 复数乘法器，利用ISE里的float IP核，实现了32位复数的乘法-Complex multiplier, using the ISE in the float IP core to achieve the 32 complex multiplications
complexadder
- 32位复数加法器，利用ISE里的float IP核-32 complex adder, using the ISE in the float IP core
IP_COE_Abs2Rel
- 编程辅助软件，将Xilinx ISE 14.x IP核含有的COE文件从绝对路径改成相对路径-Progrmming assisting software, Xilinx ISE 14.x IP core have COE file absolute path change into relative path