搜索资源列表
AD9648_ver
- FPGA通过SPI总线配置AD采集芯片AD9648的程序，Verilog实现 -FPGA configuration via SPI bus chip AD9648 AD acquisition procedures, Verilog realization
FPGA_SPI
- 本源码是用verilog语言编写的FPGA的SPI主机代码，可以用做SPI开发参考。-The source code is written in verilog FPGA SPI master code, can be used to develop a reference SPI.
MAX121_test
- max121，ad采集芯片，spi接口，fpga测试逻辑，verilog语言-max121, ad capture chip, spi interfaces, fpga test logic, verilog language
spi_cbb
- 基于FPGA设计，verilog语言变成的，SPI通用接口模块，顶层已封装成类似标准的FIFO接口；提供仿真文件；仿真器为modelsim10.0c，波形观察debussy。-Based on the FPGA design, Verilog language into a, SPI universal interface module, the top has been packaged into a FIFO interface similar to that of the standard
FPGA_51
- 51+FPGA架构的通讯口扩展,用verilog语言编写，扩展了Ｉ２Ｃ，ＳＰＩ，ＲＳ２３２。-51+ FPGA architectures communication port expansion, with verilog language, extends the I2C, SPI, RS232.
SPI_Core_2
- 用Verilog HDL 语言编写的，可在FPGA上实现的SPI总线主端 收发读写模块 -SPI Master Read-Write controller core which was Writted by Verilog HDL based on fpga
HAPF_SLAVE2
- 高压链式SVG控制用FPGA的verilog程序,其中包括SPI，16路SCI同步通讯模块程序，保护自锁功能程序，基于滞环的无功功率检测和补偿策略；还包括FPGA和DSP之间通过总线方式进行数据的快速交互等；程序完整-SVG high voltage chain of verilog FPGA control procedures, including SPI, 16 road SCI synchronous communication module procedures to protect
spihost
- fpga spi 串口 Verilog-fpga spi Verilog
MCU2FPGA_SPI_TB
- 本程序使用Verilog语言实现了SPI接口的设计，可以直接烧到FPGA实现与MCU的通信,自带有测试文件。-The program uses the Verilog language design SPI interface, you can burn directly communicate with the FPGA, MCU, comes with a test file.
Test_96_Right2
- MCU配合FPGA控制驱动96路电机,其中MCU与FPGA间用SPI通信，本文件为FPGA部分verilog源程序-MCU with FPGA control and drive motors ，where MCU communicate with FPGA using SPI
Receiver
- FPGA SPI串行收发数据全双工程序开发，使用Verilog HDL开发语言-FPGA SPI serial port to send and receive data all double engineering sequence development, using Verilog HDL language development
spi_module
- 使用FPGA编辑Verilog语言来实现控制SPI，完成SPI时序，并在该时序下实现数据的传输和接收。-FPGA and SPI
spi_master
- 使用verilog语言实现FPGA下的SPI的主机模式，波特率为晶振时钟的五分之一，发送稳定-Using verilog language to achieve the SPI under the host mode, the baud rate is one-fifth of the crystal clock, send stable
tinycpufiles
- TinyCPU源码,使用Verilog编写的资源占用极少的CPU。Quartus工程，可跑在Altera MAXII CPLD上,也很方便移植到其他FPGA上。CPU使用200个逻辑单元，外设(SPI,LCD等)使用180个逻辑单元。 内含汇编编译器源码(VC2008)，可编译CPU对应的汇编文件。-The sourcecode of TinyCPU, which only consumed very few logical cells, written by Verilog. It is
ad9787
- FPGA上与AD9787进行spi通信的verilog HDL,VHD....等例程(SPI AD9787 communication routines)
ad5781
- 用于开发dac-ad5781的verilog子程序，可用fpga开发板通过SPI进行通信