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Timer
- 嵌入式系统的单片集成定时器的Verilog实现。可实现多种配置模式，可作为通用的定时器设计模板-This is a standed timer for an SOC design.It can realize multible function need to design an micro process circut
digital-clock-
- 本代码采用verilog HDL语言编写。实现的是数字跑表计时功能-The code using verilog HDL language. Implementation is a digital stopwatch timer functions
reaction-timer
- reaction timer by verilog
basketball
- Verilog编写的篮球比赛24秒计时器，有复位、暂停等功能-Written in Verilog basketball game 24 seconds timer, a reset, and pause
timer
- verilog秒表fpga 4位数码管显示-verilog digital display stopwatch 4
TIMER
- SOPC 系统集成编译的TIMER IP核 Verilog代码-timer ip core in SOPC
timer
- 用verilog 实现时钟的功能，并在DE2开发板上调试-Clock with verilog and debug on the DE2 board
timer
- 在nios环境下，结合verilog语言开发，功能是结合系统定时器的流水灯操作-Nios environment, combined with the verilog language development is a combination of water of the system timer lamp operating
digital-Timer
- 数字时钟，使用Verilog实现，已经调试过了-Digital clock, using Verilog implementation
microwave-oven-timer
- 微波率定时器设计方案，使用verilog hdl编写-microwave oven timer design ，using verilog hdl
Timer
- Verilog编写的多功能秒表，Quartus仿真及硬件测试通过。-Verilog prepared by the multi-function stopwatch, Quartus simulation and hardware testing through.
digital-timer
- 数字时钟的verilog代码，以仿真编译通过，可直接用-Digital clock verilog code which is compiled and simulated and can be directly used
TIMER
- FPGA verilog 秒表TIMER功能-FPGA verilog THIS IS A TIMER
timer
- 本代码用verilog语言描述，在nios上操作，实现了定时器的设置和中断操作，并结合timestamp读取程序运行的时间。-The code to use verilog language to describe, in nios on operation, to achieve the timer settings and interrupt operation, combined with the timestamp reads the program run.
ReactionTimer
- Reaction Timer verilog code, can be downloaded on texas NEXYS2 or NEXYS3 board to test the reaction time by pressing the buttons.
Timer
- 基于verilog xilinx spartan 3e100的秒表计时器-Based verilog xilinx spartan 3e100 stopwatch timer
pwm.tar
- PWM Timer Verilog Design
timer
- 使用VERILOG實現時鐘,並附上TB供測試-Use VERILOG realize the clock, along with tests for TB
TIMER
- 用Verilog语言模拟的数字时钟的功能，时分秒工能都有，适合做毕设，完整工程-Verilog language simulation of the digital clock function, the time of the second division of the work can be, for the completion of the project, complete
timer
- 使用Verilog编程的秒表，使用basys2板子，同时支持两个秒表计时，有暂停复位功能，计时在七段数码管上显示。-Using Verilog programming stopwatch, use basys2 board, while supporting the two stopwatch with pause reset function, time on the seven-segment LED display.