搜索资源列表
uart-verilog-vhdl
- 拿verilog和vhdl编写的串口通信代码(可综合)-with vhdl and verilog prepared by the serial communication code (synthesis)
uart
- this a Uart source code using Verilog.
UART
- verilog代码，串口发送接收代码，含有源代码和测试文件，准确可用-verilog code for serial port transmit and receive code, with source code and test files, and accurate available
fpga_uartrw
- FPGA的uart控制器的verilog源程序，在cyclone II EP2C8Q208上调试运行成功-FPGA s UART controller Verilog source code, in cyclone II EP2C8Q208 debugging run successfully
test_uart
- uart VHDL code : include tx,rx,parity bit control
lab3
- verilog source code for uart design
UARTtransmitter
- UART Transmitter. VHDL code and its testbench.
uart
- this file contains verilog code of uart file
cp_uart_6
- 用CPLD驱动UART转USB芯片CP2102的verilog代码，与PC通信 包括CP2102的配置 驱动等-Using CPLD to drive the USB-UART CP2102 interface. verilog code, then communicate with PC, including the configuration and drivers, etc.
MCU_FPGA_Interface
- msp430单片机用IO口模拟总线时序，与FPGA进行交互的程序，附源代码，verilog，有简单文档。-msp430 I single-chip analog IO bus with timing, with the FPGA interactive process, with the source code, verilog, a simple document.
URAT_VHDL_CODE
- altera公司的fpga源代码，用VHDL编写的uart程序。-altera' s fpga source code, uart program written using VHDL.
uart_rx
- Tcode is in VERILOG HDL (Hardware descr iption language) code is of UART (universal asynchronous receiver&transmitter) receiver . its objective is to accept serial data from port of computer and allow it to come in a FPGA-Tcode is in VERILOG HDL
uart.v.tar
- uart Universal asyncronous receiver and transmitter verilog code
sdram
- 通过 UART 读写 SDRAM verilog 源代码 通过 UART 的接口发送命令来读写 SDRAM 命令格式如下： 00 02 0011 1111 2222 00： 写数据 02： 写个数 0011： 写地址 1111 2222： 写数据， 是 16 bit， 每写完一个数据，向串口发送 FF 回应； 输出： FF FF 01 03 0044 01: 读sdram 03： 读的个数 0044: 读的地址 输出： xxxx xx
UART
- this a uart verilog HDL design code-this is a uart verilog HDL design code
verilog
- 这是一个uart串口实现16550的实现，代码已测试过了。-This is a 16550 uart serial port, the code has been tested before.
Uart-Verilog
- verilog实现串口通讯，包括verilog代码和testbench代码-verilog serial communication, including the verilog code and testbench Code
uart(Verilog)
- uart 测试源码，已经测试过，非常好用-uart test code
UART_source_code
- uart verilog code for nexys2 fpga borad
uart
- FPGA Verilog设计UART通讯程序(UART communication code with Verilog in FPGA)