文件名称:sdram
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- 上传时间:2012-11-16
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文件大小:14kb
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通过 UART 读写 SDRAM verilog 源代码
通过 UART 的接口发送命令来读写 SDRAM
命令格式如下:
00 02 0011 1111 2222
00: 写数据
02: 写个数
0011: 写地址
1111 2222: 写数据, 是 16 bit, 每写完一个数据,向串口发送 FF 回应;
输出: FF FF
01 03 0044
01: 读sdram
03: 读的个数
0044: 读的地址
输出: xxxx xxxx xxxx
sdram 在 0044 0045 0046 处的数据;
sdram 使用的是 K4S161622D.pdf
系统时钟 25m, 通过 PLL 得到 SDRAM clk 100m
sdram controller clk 100m, 前者相对后者2ns 相移 -Read and write through the UART SDRAM verilog source code through the UART interface to send commands to SDRAM read and write command format is as follows: 0,002,001,111,112,222 00: Write Data 02: Write the number of 0011: write address 11112222: write data, is 16 bit, each completed a data, respond to the serial port FF output: FF FF 01 03 0044 01: Reading sdram 03: 0044 the number of read: Read the address output: xxxx xxxx xxxx sdram at 004,400,450,046 at the data sdram use system clock is K4S161622D.pdf 25m, obtained by PLL SDRAM clk 100m sdram controller clk 100m, the former phase shift relative to the latter 2ns
通过 UART 的接口发送命令来读写 SDRAM
命令格式如下:
00 02 0011 1111 2222
00: 写数据
02: 写个数
0011: 写地址
1111 2222: 写数据, 是 16 bit, 每写完一个数据,向串口发送 FF 回应;
输出: FF FF
01 03 0044
01: 读sdram
03: 读的个数
0044: 读的地址
输出: xxxx xxxx xxxx
sdram 在 0044 0045 0046 处的数据;
sdram 使用的是 K4S161622D.pdf
系统时钟 25m, 通过 PLL 得到 SDRAM clk 100m
sdram controller clk 100m, 前者相对后者2ns 相移 -Read and write through the UART SDRAM verilog source code through the UART interface to send commands to SDRAM read and write command format is as follows: 0,002,001,111,112,222 00: Write Data 02: Write the number of 0011: write address 11112222: write data, is 16 bit, each completed a data, respond to the serial port FF output: FF FF 01 03 0044 01: Reading sdram 03: 0044 the number of read: Read the address output: xxxx xxxx xxxx sdram at 004,400,450,046 at the data sdram use system clock is K4S161622D.pdf 25m, obtained by PLL SDRAM clk 100m sdram controller clk 100m, the former phase shift relative to the latter 2ns
相关搜索: uart verilog
串口 Verilog
verilog 串口
sdram verilog
sdram UART
Verilog sdram
pll
sdram
格式 verilog
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下载文件列表
pll_ctrl.v
pll_ctrl_bb.v
pll_ctrl_syn.v
sdr_ctrl.v
sdr_param.v
sdr_test_top.sdc
sdr_test_top.v
sys_ctrl.v
uart_clk.v
uart_recv.v
uart_send.v
uio_ctrl.v
pll_ctrl_bb.v
pll_ctrl_syn.v
sdr_ctrl.v
sdr_param.v
sdr_test_top.sdc
sdr_test_top.v
sys_ctrl.v
uart_clk.v
uart_recv.v
uart_send.v
uio_ctrl.v
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