搜索资源列表
xilinx_uart_vhdl
- 这是xilinx公司的uart源代码，希望对需要的朋友有所帮助
__FPGA_Prototyping_by_VHDL_Examples
- 在赛灵斯上用VHDL实现，串口，PS MOUSE, PS KEYBOARD..... 协议-on Xilinx,to achieve using VHDL too fullfill UART, PS MOUSE, PS KEYBOARD ..... prototype
fpga
- fpga数字电子系统设计与开发 ISE I2C UART usb vga -ISE I2C UART usb vga
FPGA_RS232
- 为增加系统稳定性，减小电路板面积，提出一种基于FPGA的异步串行口IP核设计。该设计使用VHDL硬件描述语言时接收和发送模块在Xilinx ISE环境下设计与仿真。最后在FPGA上嵌入UART IP核实现电路的异步串行通信功能。该IP核具有模块化、兼容性和可配置性，可根据需要实现功能的升级、扩充和裁减。-In order to increase system stability, reduce board space, presents a FPGA-based asynchronous ser
verilog_rs232
- 用verilog实现串行口UART控制器，适用于XILINX器件-verilog UART controller
uart550_examples
- uart 550 chip example on xilinx board
UART-Communication
- Xilinx FPGA UART communication code
uart1
- vhdl uart module. this file is used to transfer programs frm fpga xilinx spartam 3e kit to desktop pc through rs232 serial port.
uart
- XILINX参考设计，uart，包括modelsim测试代码-XILINX reference design, uart, including modelsim test code
UART
- 一个高速串口 使用查找表写的 很省资源 来自xilinx picoblaze代码-A high-speed serial port using a lookup table to write the provincial resources
uart
- xilinx板子virtex5板子上实现rs232串口通信实验，并通过led灯进行检测-xilinx the board virtex5 board rs232 serial communication experiment to detect and led through the lights
uart
- Code VHDL/Verilog for UART FPGA: Xilinx, Altera-Code VHDL/Verilog for UART FPGA: Xilinx, Altera...
uart
- 基于XILINX+ISE的通用串行总线设计-Design based on the Universal Serial Bus XILINX+ISE
UART-Verilog-source
- Verilog编写UART串口例程，实现FPGA与上位机串口通信，利用ASCII码进行大小写转换，在Xilinx Virtex-5开发板测试通过-UART serial routines written in Verilog, FPGA serial communication with the host computer using the ASCII code case conversion, in the Xilinx Virtex-5 development board test
UART
- Verilog HDL编写的串口程序实例，很详细好用的参考代码。针对Xilinx FPGA开发板，在Xilinx ISE编译调试成功，串口开发的经典例程。-Verilog HDL serial program written examples, very good reference code in detail. In view of the Xilinx FPGA development board, in Xilinx ISE compiler debugging success, a s
uart
- 利用xilinx 公司的ise软件基于verilog HDL实现UART控制程序-based on the xilinx ise and use verilog HDL language to achieve the purposes that control the uart.
Uart
- Adding flow control to uart core of xilinx
verilog-uart-master
- Verilog TUTORIAL for beginners. We had earlier published a Verilog tutorial that made use of the Xilinx ISE Simulator.
xapp223-PDF
- 200 MHz UART with Internal 16-Byte Buffer - XAPP223 XILINX