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etd-0407109-183702-81-001[1]
- 文章介绍了YUV向RGB颜色空间转换的硬件电路实现算法.在高基乘法算法基础上,建立了参数化高基乘法算法模型,并给出了Verilog HDL描述 小数乘法的整数乘法近似和近似误差给予了详细的讨论.采用乘法单元复用的设计结果将在两个时钟周期内完成YUV向RGB的颜色空间转换.-This paper introduces the YUV to RGB color space conversion hardware algorithm. Matrix multiplication algorithm i
Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Ex
- 来自于ALTERA官方网站。 本文档详细介绍怎样利用MAX® II CPLD 来实现脉冲宽度调制(PWM)。本设计还利用了MAX II CPLD 的内部用户闪存振荡器，不需要采用专门的外部时钟。 附有verilog源程序。-From ALTERA website. This document details how to use the MAX ® II CPLD to implement pulse width modulation (PWM). This design
CPU
- 一个完整的流水CPU设计，quartus平台，Verilog实现-CPU design a complete water, quartus platform, Verilog realization
BeijingUniversityTutorialforVerilog
- Verilog超详细教程，北大微电子系硬件设计入门教程。-Super detailed tutorial Verilog, hardware design, Department of Microelectronics, Peking University Tutorial.
hdb3
- verilog的HDB3编码设计，求点数
verilog
- 关于数字系统设计的Verilog教程，是一本既有理论又有实践的设计大全。-Verilog digital system design on the tutorial, is a theoretical and practical design both Daquan.
CRC
- CRC校验参考设计Verilog代码 包括所有代码-Verilog code for CRC check reference design includes all the code
verilog
- 无线通信用verilog代码，超全，可用来做基本设计-Verilog code for wireless communications, ultra wide, can be used for basic design
lcd
- SPARTAN 3E 开发板驱动程序 Verilog源码 对于数字电路设计是很好的参考资料-SPARTAN 3E development board driver for digital circuit design, Verilog source code is a good reference
22_multi_speed_filter
- 基于FPGA的多速率滤波器的设计，verilog设计的，QII开发环境-FPGA-based multi-rate filter design, verilog design, QII development environment
cordic
- cordic的verilog设计，qII实现，比较简单，讲诉了算法的实现过程。-cordic the verilog design, qII implementation, relatively simple complaints about the implementation process of the algorithm.
WirelesscommunicationFPGAdesign.Verilog
- 无线通信FPGA设计[田耘等编著][程序源代码]_2010112514154616，用Xilinx开发，调用modelsim进行仿真。-Wireless communication FPGA design [TianYun, etal] [source code] _2010112514154616, use Xilinx development, call modelsim simulation.
wavelet
- 基于DB8小波变换的verilog代码设计，支持Avalon总线-Verilog DB8 Wavelet Transform Based on code design, support Avalon bus
FifoAndTestbench
- 这是一个verilog编写的同步fifo和testbench的设计-It is a synchronous fifo and testbench design with verilog
USB3.0specification(chinese)
- USB3.0的中文技术规范，包含结构规范和电气规范，适合英文不佳的工程师参考设计。-Chinese USB3.0 specification, including structural and electrical specifications for reference design engineers with poor English.
DE1-Practice-VGA-display-
- 用altera的fpga设计的DE1开发板作为硬件平台实现VGA显示，verilog实现的，8种色彩，作为fpga驱动vga液晶的入门。DE1实践之VGA显示（8bit色彩）-Altera fpga design with the DE1 board as a hardware platform development VGA display, verilog implementation, 8 colors, as the introduction to fpga driver vga LCD
electronic-piano
- VERILOG HDL电子琴设计的源代码-VERILOG HDL source organ
verilog-very-important
- 本书中文编写，详细介绍了verilog语言，并运用实例设计经典的电路。本书实用而又易懂。-Book written in Chinese, detailing the verilog language, and use the classic example of the circuit design. Book practical and easy to understand.
SDH1
- SHD 详细设计,包含各种文档，以及VERILOG 源代码-SHD detailed design, including all documents
Verilog-HDLTOP-DOWN
- 用Verilog HDL的建模来设计一个经简化的只有八条指令、字长为一字节的RISC中央处理单元（CPU）的顶层设计。-Modeling with the Verilog HDL to design a simplified and only eight instructions, word length is a byte RISC central processing unit (CPU) of the top-level design.