搜索资源列表
QuartusII-for-chinese
- verilog设计练习进阶,很好的练习资料-Advanced verilog design practice, good practice information ,,,,,,,
controller-design-of-sdram-
- 基于FPGA对sdram控制器的设计（VERILOG语言）-FPGA-based controller design of sdram (VERILOG language)
rs232
- verilog语言编写，RS232通讯程序设计-verilog language, RS232 Communication Program Design
Verilog
- 一些关于Verilog分频器设计.doc-Verilog divider design. Doc
Verilog-Digital-System-Design
- Verilog数字系统设计——RTL综合.测试平台与验证 书中的所有源代码-Verilog Digital System Design- RTL synthesis. Test and verification platform for all the source code for the book
Verilog-HDL
- Verilog HDL设计的示例程序与讲解
BPSK
- 用于BPSK调制的自行设计，说明如下： 1.matlab.txt中的程序是matlab平台下的.mat格式。目的是输出一个64*4的矩阵，矩阵的每个元素都为0~255间的整数。矩阵每行的四个数是一个码元的四个抽样点的量化值。但由于当前码元通过升余弦滤波系统时，受到前后共6个码元的共同影响，所以是由6个码元共同决定。这6个码元是随机的，可能是0也可能是1（双极性时可能是-1也可能是+1），故6个码元共2^6=64种情况，所以产生的矩阵是64*4。最后逐行输出这256个数。 2.
Verilog
- Verilog数字系统设计教程（夏宇闻）-Verilog Digita system design manual
Verilog-HDL
- Verilog HDL程序设计教程,是非常适合Verilog HDL语言的初学者的入门教程，里面详细介绍了语法、结构等方面。-Verilog HDL programming tutorial, Verilog HDL language is very suitable for beginners introductory tutorial, which introduces grammar, structure, and so on.
adc
- 设计ADC控制器，Verilog代码.利用有限状态机设计方法在FPGA上设计ADC0809的接口控制器，采样结果送到数码管显示出来。-ADC controller design, Verilog code using finite state machine design in the FPGA design ADC0809 interface controller, the sampling results to the digital display.
dianzimimasuo
- 采用verilog设计，7段数码管进行输入的显示，在DE-2平台上进行密码锁的实现。-Using verilog design, 7-segment LED display for input in the DE-2 platform on the lock implementation.
SDI_PassThr_SZ
- Xilinx SDI参考设计，Verilog/VHDL源代码和相关文档等-Xilinx SDI pass through Verilog/VHDL source code
shift194
- 194的Verilog设计，比较简洁的一种设计思路-194 of the Verilog design, a relatively simple design ideas
code
- <基于Verilog HDL的通信系统设计>源码，包含ASK,FSK,PSK,QPSK,PPM等的调制解调-< Verilog HDL-based communication system design> source, including ASK, FSK, PSK, QPSK, PPM and other modem
Verilog
- QuartusII编译与仿真之warning解析,设计示例,verilog中reg和wire类型的区别.-QuartusII compilation and simulation of warning analysis, design example, verilog in the difference between reg and wire type.
Verilog-HDL--design-skill
- 该文档很好的介绍了verilog的设计方法，讲的比较详细，希望对读者有帮助-A good introduction to the document verilog design methodology, speaking in more detail, hope to help readers
Verilog
- 里面有一些FPGA设计的常用模块，已经做好 立刻调用即可 -There are some common FPGA design module, ready to immediately call
Verilog
- 好的源代码 是你学习数字系统设计的重要资料 你的好帮手-Good source code is that you learn the importance of digital information systems design your good helper
VerilogDesignand-test_PdfPCode
- Verilog 设计与验证源码+PDF，经典教程，对与RTL和状态机的理解有很大帮助，适合FPGA开发工程师。-Verilog design and verification source+ PDF, classic tutorial, and state machine understanding of RTL helps a lot, suitable for the FPGA development engineers.
1day11-keyboard
- 清华大学电子课程设计：Verilog语言编写，可在QuartusII完全正确运行，FPGA下载，键盘按键输出相对应数字，有防抖功能-Verilog language, can be run in QuartusII entirely correct, FPGA download, keyboard keys corresponding to the output figures, anti-shake function