搜索资源列表
61EDA_C2111
- 数字下变频设计。 在ALTERA的QUARTUS ii下实现。实用，好用。--Verilog language implementation of the digital do
timing_analysis_1.pdf
- altera 公司有关time analysis 的文档...对于verilog初学者以及编程格式规范化有很大的帮助.-altera company documents on time analysis ... beginners and verilog programming format for the standardization of great help.
I2C
- 本源代码中用Verilog HDL语言编写了I2C的顶层及子模块文件，详细完整，并在Altera实验板上得以验证-primitive code discribe the I2C s function using the Verilog HDL language, the code are particular and integrity,moreover it has been validated in the altera FPGA and passed
VerilogCode_7_segment_decoder
- Verilog Code for seven segment decoder for the code to be implemented on Altera DE2 board
VerilogCode_8-bit_2to1_mux
- Verilog Code for 8 to 1 multiplexer for the code to be implemented on Altera DE2 board
VerilogCode_BCD_counter
- Verilog Code for a BCD counter and it is implemented on Altera DE2 board-Verilog Code for a BCD counter and it is implemented on Altera DE2 board
Verilog_USB_IN
- USB in 模型，作为输入，包括基于Altera的工程、源码、固件，使用Verilog-USB in model, as input, including the Altera-based project, source code, firmware, Verilog
tutorial
- another verilog VHDL tutorial, targeting altera DE2 board, but very intuituve.
DE2_Default
- Altera DE2 demonstration design, lot of interesting verilog code for synthesis
cam
- It is a VERILOG program for interfacing the 5Megapixel camera module in ALTERA DE2 CYCLONEII board.
IR
- 利用verilog编写的红外线接收解码电路，开发环境为altera板，quartusII仿真并在开发板上验证通过-Prepared using verilog infrared receiver decoder circuit, the development environment for the altera board, quartusII simulation and validated by the development board
digi_clock
- 用verilog写的数字钟程序，已在altera公司的cyclone IV开发板上运行成功，很有价值-Digital clock using verilog written procedures for the company in altera cyclone IV development board to run a successful, valuable
final
- This Source is Verilog Coding. Made in Altera Quartus 9.0 Service Pack 3. Important, I know not used board.
sdr
- 全数字OQPSK解调算法的研究及FPGA实现 论文介绍了OQPSK全数字接收解调原理和基于 软件无线电设计思想的全数字接收机的基本结构，详细阐述了当今OQPSK数字 解调中载波频率同步、载波相位同步、时钟同步和数据帧同步的一些常用算法， 并选择了相应算法构建了三种系统级的实现方案。通过MATLAB对解调方案的 仿真和性能分析，确定了FPGA中的系统实现方案。在此基础上，本文采用Verilog HDL硬件描述语言在Altera公司的QuartusⅡ开发平台上设计
07_piano
- altera FPGA 教程 电子琴 verilog 语言 实现-a piano basied on FPGA ! It is a good thing!
sixiangzaibosheji
- 本代码采用Altera公司的FPGA为主控芯片，以开发软件QuartusⅡ为工具。采用EDA设计中的自顶向下与层次式设计方法使用精简的DDS算法完成了输入为14MHz，输出四路频率为70MHz的四相序正弦载波（相位分别为0°、90°、180°、270°）的设计。利用Verilog HDL语言进行了程序设计并用QuartusⅡ对设计进行了仿真，验证了其正确性。-DDS algorithm with simplified input for the completion of 14MHz, 70M
SDR_SDRAM_IP
- SDR SDRAM 控制器，Altera官网重要资料。内涵说明文档，和VHDL与Verilog两种设计IP。-SDR SDRAM controller from Altera
lcd1602
- 用verilog语言写的关于1602液晶显示器的调试程序，芯片用的是Altera公司的，有需要的可以看看！-Written language with verilog 1602 LCD on the debugger, the chip using Altera' s, need to look at!
clock_1Hz
- Clock 1Hz with duty cycle control for verilog for DE2-115 Altera FPGA
ones_counter
- Ones counter for Verilog, basic project for Altera FPGA