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文件名称:SDR_SDRAM_IP

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [PDF]
  • 上传时间：
    2012-11-16
  • 文件大小：
    2.25mb
  • 已下载：
    0次
  • 提 供 者：
    peter*****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
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修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

SDR SDRAM 控制器，Altera官网重要资料。内涵说明文档，和VHDL与Verilog两种设计IP。-SDR SDRAM controller from Altera
相关搜索： sdr_sdram sdr sdram ip

(系统自动生成,下载前可以参看下载内容)

下载文件列表

SDR_SDRAM_IP/sdr_sdram.pdf
SDR_SDRAM_IP/verilog/doc/readme.txt
SDR_SDRAM_IP/verilog/doc/sdr_sdram.pdf
SDR_SDRAM_IP/verilog/model/mt48lc8m16a2.v
SDR_SDRAM_IP/verilog/route/PLL1.v
SDR_SDRAM_IP/verilog/route/sdr_sdram.csf
SDR_SDRAM_IP/verilog/route/sdr_sdram.esf
SDR_SDRAM_IP/verilog/route/sdr_sdram.vqm
SDR_SDRAM_IP/verilog/simulation/modelsim.ini
SDR_SDRAM_IP/verilog/simulation/readme.txt
SDR_SDRAM_IP/verilog/simulation/sdr_sdram_tb.v
SDR_SDRAM_IP/verilog/simulation/work/altclklock/verilog.psm
SDR_SDRAM_IP/verilog/simulation/work/altclklock/_primary.dat
SDR_SDRAM_IP/verilog/simulation/work/altclklock/_primary.vhd
SDR_SDRAM_IP/verilog/simulation/work/command/verilog.psm
SDR_SDRAM_IP/verilog/simulation/work/command/_primary.dat
SDR_SDRAM_IP/verilog/simulation/work/command/_primary.vhd
SDR_SDRAM_IP/verilog/simulation/work/control_interface/verilog.psm
SDR_SDRAM_IP/verilog/simulation/work/control_interface/_primary.dat
SDR_SDRAM_IP/verilog/simulation/work/control_interface/_primary.vhd
SDR_SDRAM_IP/verilog/simulation/work/mt48lc8m16a2/verilog.psm
SDR_SDRAM_IP/verilog/simulation/work/mt48lc8m16a2/_primary.dat
SDR_SDRAM_IP/verilog/simulation/work/mt48lc8m16a2/_primary.vhd
SDR_SDRAM_IP/verilog/simulation/work/pll1/verilog.psm
SDR_SDRAM_IP/verilog/simulation/work/pll1/_primary.dat
SDR_SDRAM_IP/verilog/simulation/work/pll1/_primary.vhd
SDR_SDRAM_IP/verilog/simulation/work/sdr_data_path/verilog.psm
SDR_SDRAM_IP/verilog/simulation/work/sdr_data_path/_primary.dat
SDR_SDRAM_IP/verilog/simulation/work/sdr_data_path/_primary.vhd
SDR_SDRAM_IP/verilog/simulation/work/sdr_sdram/verilog.psm
SDR_SDRAM_IP/verilog/simulation/work/sdr_sdram/_primary.dat
SDR_SDRAM_IP/verilog/simulation/work/sdr_sdram/_primary.vhd
SDR_SDRAM_IP/verilog/simulation/work/sdr_sdram_tb/verilog.psm
SDR_SDRAM_IP/verilog/simulation/work/sdr_sdram_tb/_primary.dat
SDR_SDRAM_IP/verilog/simulation/work/sdr_sdram_tb/_primary.vhd
SDR_SDRAM_IP/verilog/simulation/work/_info
SDR_SDRAM_IP/verilog/source/altclklock.v
SDR_SDRAM_IP/verilog/source/Command.v
SDR_SDRAM_IP/verilog/source/compile_all.v
SDR_SDRAM_IP/verilog/source/control_interface.v
SDR_SDRAM_IP/verilog/source/Params.v
SDR_SDRAM_IP/verilog/source/PLL1.v
SDR_SDRAM_IP/verilog/source/sdr_data_path.v
SDR_SDRAM_IP/verilog/source/sdr_sdram.v
SDR_SDRAM_IP/verilog/synthesis/synplicity/sdr_sdram.prj
SDR_SDRAM_IP/vhdl/doc/readme.txt
SDR_SDRAM_IP/vhdl/doc/sdr_sdram.pdf
SDR_SDRAM_IP/vhdl/model/io_utils.vhd
SDR_SDRAM_IP/vhdl/model/mt48lc8m16a2.vhd
SDR_SDRAM_IP/vhdl/model/mt48lc8m16a2.zip
SDR_SDRAM_IP/vhdl/model/mti_pkg.vhd
SDR_SDRAM_IP/vhdl/model/stdlogar.vhd
SDR_SDRAM_IP/vhdl/model/util1164.vhd
SDR_SDRAM_IP/vhdl/route/pll1.vhd
SDR_SDRAM_IP/vhdl/route/sdr_sdram.csf
SDR_SDRAM_IP/vhdl/route/sdr_sdram.esf
SDR_SDRAM_IP/vhdl/route/sdr_sdram.vqm
SDR_SDRAM_IP/vhdl/simulation/APEX20KE_MF.VHD
SDR_SDRAM_IP/vhdl/simulation/io_utils.vhd
SDR_SDRAM_IP/vhdl/simulation/lpm_pack.vhd
SDR_SDRAM_IP/vhdl/simulation/modelsim.ini
SDR_SDRAM_IP/vhdl/simulation/mt48lc8m16a2.vhd
SDR_SDRAM_IP/vhdl/simulation/mti_pkg.vhd
SDR_SDRAM_IP/vhdl/simulation/readme.txt
SDR_SDRAM_IP/vhdl/simulation/sdr_sdram_tb.vhd
SDR_SDRAM_IP/vhdl/simulation/stdlogar.vhd
SDR_SDRAM_IP/vhdl/simulation/util1164.vhd
SDR_SDRAM_IP/vhdl/simulation/work/altcam/behave.dat
SDR_SDRAM_IP/vhdl/simulation/work/altcam/behave.psm
SDR_SDRAM_IP/vhdl/simulation/work/altcam/_primary.dat
SDR_SDRAM_IP/vhdl/simulation/work/altclklock/behavior.dat
SDR_SDRAM_IP/vhdl/simulation/work/altclklock/behavior.psm
SDR_SDRAM_IP/vhdl/simulation/work/altclklock/_primary.dat
SDR_SDRAM_IP/vhdl/simulation/work/altlvds_rx/behavior.dat
SDR_SDRAM_IP/vhdl/simulation/work/altlvds_rx/behavior.psm
SDR_SDRAM_IP/vhdl/simulation/work/altlvds_rx/_primary.dat
SDR_SDRAM_IP/vhdl/simulation/work/altlvds_tx/behavior.dat
SDR_SDRAM_IP/vhdl/simulation/work/altlvds_tx/behavior.psm
SDR_SDRAM_IP/vhdl/simulation/work/altlvds_tx/_primary.dat
SDR_SDRAM_IP/vhdl/simulation/work/command/rtl.dat
SDR_SDRAM_IP/vhdl/simulation/work/command/rtl.psm
SDR_SDRAM_IP/vhdl/simulation/work/command/_primary.dat
SDR_SDRAM_IP/vhdl/simulation/work/control_interface/rtl.dat
SDR_SDRAM_IP/vhdl/simulation/work/control_interface/rtl.psm
SDR_SDRAM_IP/vhdl/simulation/work/control_interface/_primary.dat
SDR_SDRAM_IP/vhdl/simulation/work/io_utils/body.dat
SDR_SDRAM_IP/vhdl/simulation/work/io_utils/body.psm
SDR_SDRAM_IP/vhdl/simulation/work/io_utils/_primary.dat
SDR_SDRAM_IP/vhdl/simulation/work/io_utils/_vhdl.psm
SDR_SDRAM_IP/vhdl/simulation/work/mt48lc8m16a2/behave.dat
SDR_SDRAM_IP/vhdl/simulation/work/mt48lc8m16a2/behave.psm
SDR_SDRAM_IP/vhdl/simulation/work/mt48lc8m16a2/_primary.dat
SDR_SDRAM_IP/vhdl/simulation/work/mti_pkg/body.dat
SDR_SDRAM_IP/vhdl/simulation/work/mti_pkg/body.psm
SDR_SDRAM_IP/vhdl/simulation/work/mti_pkg/_primary.dat
SDR_SDRAM_IP/vhdl/simulation/work/mti_pkg/_vhdl.psm
SDR_SDRAM_IP/vhdl/simulation/work/pll1/syn.dat
SDR_SDRAM_IP/vhdl/simulation/work/pll1/syn.psm
SDR_SDRAM_IP/vhdl/simulation/work/pll1/_primary.dat
SDR_SDRAM_IP/vhdl/simulation/work/sdr_data_path/rtl.dat
SDR_SDRAM_IP/vhdl/simulation/work/sdr_data_path/rtl.psm
SDR_SDRAM_IP/vhdl/simulation/work/sdr_data_

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