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mult8_csdn
- 用verilog语言编写的8位乘法器，完成了8位二进制的整数乘法，供大家参考-Verilog language with 8-bit multiplier, completed the 8-bit binary integer multiplication, for your reference
frequency_divide
- 本程序用verilog编写，实现了任意整数分频-Arbitrary integer frequency_divider
5956447divider
- 基于srt-2算法，利用verilog实现16位定点无符号数除法器（除数、被除数均由16位整数和16位小数组成，商由32位整数和16位小数构成，余数由32位小数组成）-Based on srt-2 algorithm, using verilog to achieve 16-bit fixed-point unsigned divider (divisor, dividend by 16-bit integer and 16-bit decimal form, business from the
verilog_std_div
- Verilog HDL语言实现任意整数分频.只需调节分频数和分频位宽即可。-Verilog HDL language to any integer divider. Simply adjust the number and frequency can be frequency division-bit wide.
SQRT
- 用verilog代码编写的求整数平方根的FPGA工程。-Verilog code written request with the integer square root of the FPGA project.
8bitclk_div
- 任意整数分频计,verilog编写，仿真通过-Any integer frequency meter
div
- 32位整数阵列除法器，verilog代码编写，性能高效。-32-bit integer array divider, verilog coding, performance and efficient.
Gradientascent1
- 2个整数的加法运算，有verilog语言编写-Two integer addition operation
INT_DCT
- Verilog HDL语言实现的整数DCT变换模块。其中包括一维和两维的DCT变换模块各一个。该模块都通过硬件仿真以及FPGA实现后的测试，均满足预期的DCT变换功能。-Integer DCT transfer module with Verilog HDL format. The package includes one 1-D and one 2-D DCT transfer module, which all pass simulation and FPGA evaluation.
div_any
- 任意整数N分频器的verilog代码，N需要代码中进行设置-Any integer N divider verilog code N need to code set
fenpin
- verilog语言编写的分频程序，可以通过defpram实现任意整数任意占空比分频，有详细注释-divider verilog language program can be achieved through defpram arbitrary integer divide any duty, detailed notes
signed_integer_divider_latest.tar
- VERILOG IMPLEMENTATION OF SIGNED INTEGER DIVIDER
divider_32bitdivby16bit
- verilog代码实现的32位除以16位无符号整数除法器，在别人8位除法器的基础上改进完成，32个时钟周期完成一次运算。-verilog code for 32-bit divided by 16-bit unsigned integer divider it s based on other guy s 8 bit divider verilog code. it need 32 clock cycles to complete an operation.
gen_divd
- FPGA分频器，verilog语言版本，通过实例化参数实现任意整数倍分频-FPGA divider, verilog language version, by instantiating an arbitrary integer multiple parameters Divide
frequency-divider
- 用VERILOG 语言写的数控分频器，可能输入时钟信号实现任意整数倍的分频，-NC divider, with the words written in VERILOG HDL, can achieve any integer multiple of the input clock frequency, contains the entire project file.
float_int
- 自己编写的，浮点数与整数之间的转换的Verilog HDL实现-Written by myself, it is converted into Verilog HDL integer floating point implementation