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Virtex-5-FPGA-Data-Sheet
- 本程序基于xilinx fpga，v5，verilog语言，主要用于数据采集，采集频率可达500m，通过pingpang缓存进行数据转发。-The program xilinx fpga, v5, verilog language, mainly used for data acquisition, acquisition frequency of up to 500m, through data forwarding pingpang cache.
code
- 32位全加器 使用verilog写的硬件描述语言，xilinx芯片上运行过-32bits full adder
code
- 32bits流水线加法器，verilog语言的，xilinx公司芯片上运行通过-The 32bits pipelined adder verilog language, xilinx chip run through
daima
- 32bits进位选择加法器，verilog语言的，xilinx公司芯片上运行通过-The 32bits carry select adder verilog language, xilinx chip run through
daima
- 32bits提前进位加法器，verilog语言的，xilinx公司芯片上运行通过-The 32bits advance carry adder verilog language, xilinx chip run through
code
- 32bits补码加法器，verilog语言的，xilinx公司芯片上运行通过-The 32bits complement adder verilog language, xilinx chip run through
zhongzhilvbo
- xilinx ise 与modesim联合验证中值滤波 含verilog源程序和整个工程文件-the xilinx ise modesim median filter containing joint verification verilog source, and the entire project file
fpga_Uart
- 串口通信控制器 verilog实现含波特率发生模块，发送、接收模块程序以及xilinx所有工程文件-The serial communication controller verilog containing the baud rate generator module, send, receive module program xilinx all project files
trafficLED
- 实现基本交通灯的功能，Xilinx Spartan-3E实验板上基于verilog控制东西南北两组交通灯的操控。-To achieve the basic function of the traffic lights, Xilinx Spartan-3E experiment board based on verilog controlled manipulation of the North and South, East and West two sets of traffic lights
trafficLED2
- 实现基本交通灯的功能，Xilinx Spartan-3E实验板上基于verilog控制主干道和支干道东西南北两组交通灯LED的操控。-To achieve the basic function of the traffic lights, Xilinx Spartan-3E experiment board based on verilog control the handling of the North and South, East and West of the main roads a
runningclock
- verilog HDL实现跑表设计，开发环境为xilinx，fpga芯片为spartan系列。-verilog HDL the Stopwatch design and development environment for the spartan xilinx, fpga chip series.
digitalclock_demo
- 该程序适用于xilinx公司的FPGA开发板，spartan3E系列250型号 通过verilog编程实现数字钟的功能，下板子验证可用！-This procedure applies to xilinx FPGA development board Series 250 Model spartan3E digital clock verilog programming under the board to verify available!
imageprocess
- 典型的图像采集verilog代码，开发板源码-this is typical image process code,provided by xilinx developmentpacadge
JPEG-Encoder
- JPEG 编码器的verilog实现，已经在XILINX SPARTAN6上实现并验证。-The JPEG encoder verilog implementation has been implemented in a Xilinx SPARTAN6 and verify.
ICAP_FPGA_Multiboot
- 在xilinx的ml507板子上用的ICAP功能 配置存储器 这里边包含了控制程序 以及配置ICAP寄存器的程序 就是完整的通过串口控制FPGA多重配置的程序 用verilog实现的-how to configure the ICAP
LED_TEST
- Verilog的LED闪烁程序，xilinx ISE开发环境-Verilog LED flashes, Xilinx ISE development environment
spi
- spi协议 用verilog 编写 可以在xilinx fpga板子上 ise软件-spi protocol written in verilog in xilinx fpga board ise software
my_bayer2rgb
- 摄像头Bayer 转rgb信号 用verilog 编写 在xilinx fpga 软件下 ise 综合 编译-Bayer turn the camera rgb signal in xilinx fpga verilog prepared under ise integrated compiler software
I2C
- iic协议 用verilog hdl语言，可以在xilinx ise软件 编译 综合-iic agreement verilog hdl language can be compiled in xilinx ise software integrated
FIR
- 使用Verilog语言编写的FIR滤波器,在Xilinx Spartan-6上运行通过,是很好的Verlog程序-Using Verilog language FIR filter, the Xilinx Spartan-6 run through, is a very good program Verlog