搜索资源列表
Digital-VLSI-Systems-Design.pdf
- A Design Manual for Implementation of Projects on FPGAs and ASICs Using Verilog.
ALU_exercise
- 弗莱堡大学VLSI课程ALU练习，希望对大家有帮助-University of Freiburg VLSI courses ALU practice, we hope to help
tieu-luan-VLSI_huept_27042013
- Clock in design VLSI
VectCPU_1s40_0_81_nov0208
- 国外博士写向量处理机，是和NIOS处理器一起开发的，对这个的研究比较透彻，希望对大家有用-Most previous research into vector architectures has concentrated on supercomputing applications and small enhancements to existing vector supercomputer implementations. This thesis expands the body of
barreldistortionproj
- image processing in vlsi
15-vlsi
- Asynchronous fine grain power gated logic paper get code and logic static used
VLSI5
- vlsi papers low power area
ieee-(4)
- Network on chip is an emerging[when?] paradigm for communications within large VLSI systems implemented on a single silicon chip. Sgroi et al. call "the layered-stack approach to the design of the on-chip intercore communications the Network-on-Chip
arbiter-code
- this is design of an multimedia arbiter in vlsi with screen shots
vlsisp1stunit
- It focus on all the basics of vlsi concepts
divider.c
- 改良型除法器，用来模拟硬件VLSI除法器的工作步骤，是设计硬件的前序步骤-improved divider
VLSI_NEW_AUTHOR
- Enable vlsi book for any electronics vlsi enginerrEnable vlsi book for any electronics vlsi engine-Enable vlsi book for any electronics vlsi enginerrEnable vlsi book for any electronics vlsi enginerr
code
- matlab code for speech in vlsi
The_first_CoOS_program
- INTRODUCTION The course program on Verilog HDL Basics is designed for undergraduate education on “VLSI Design” specialization. The course duration is 64 hours, lectures volume is 32 hours, and laboratory works are 32 hours. COURSE GOALS AND OB
Resume
- arm vlsi verilog vhdl embedded
PART_V
- vlsi related document delete if copyrighted
Planar-integrated-optical-vector-matrix-multiplie
- We present the design of a planar-integrated optoelectronic vector-matrix multiplier. The inherent parallel-processing potential is fully exploited by optical implementation of multiplications and summations. Planar integration makes the free-spa
latch
- Abstract—Power is becoming a precious resource in modern VLSI design, even more so than area. This paper proposes a novel architecture for modular, scalable &reusable hybrid constant co-efficient multiplier (KCM) circuit. Comparison is made b
Assignment(VLSI)
- Verilog model codes for beginners
Tubes-VLSI
- 64 FFT pada program VHDL