搜索资源列表
Tri-Eth
- 采用xilinx三太以太网ip核，tri-mode MAC完成千兆以太网数据传输-Too Ethernet using xilinx ip three nuclear, tri-mode MAC Gigabit Ethernet data transmission is completed
leds
- 这是一个在xilinx的开发环境EDK上，点亮LED灯的代码示例-This is a xilinx EDK development environment, code samples, lit LED lights
latch
- Abstract—Power is becoming a precious resource in modern VLSI design, even more so than area. This paper proposes a novel architecture for modular, scalable &reusable hybrid constant co-efficient multiplier (KCM) circuit. Comparison is made b
ball_game
- VHDL VGA 弹球游戏 基于Xilinx Spartan 3E的FPGA 通过VGA显示弹球游戏-VHDL VGA pinball game is based on Xilinx Spartan 3E FPGA pinball games via VGA display
DDS
- 直接数字合成(DSS)的matlab仿真,采用simulink和Xilinx的system generator工具开发-simulink for DSS, the development tool is the system generator by Xilinx and simulink
ADPLL
- This paper presents the ADPLL design using Verilog and its implementation on FPGA. ADPLL is designed using Verilog HDL. Xilinx ISE 12.1 Simulator is used for simulating Verilog Code. This paper gives details of the basic blocks of an ADPLL. In this p
ADPLL
- This paper presents the ADPLL design using Verilog and its implementation on FPGA. ADPLL is designed using Verilog HDL. Xilinx ISE 12.1 Simulator is used for simulating Verilog Code. This paper gives details of the basic blocks of an ADPLL. In this p
powerlink
- powerlink 次站VHDL源码，可以实现4中不同的模式，基于xilinx平台。-powerlink slave VHDL sourcecode，which is based on Xilinx platform.
Codes-and-Reports
- Verilog Source code for arbitrary waveform generator- simple DDS algorithm codes run on Xilinx Spartan-3E fpga to show output on dac pin. Please see the included report. its really simple to implement. all source code is given.
piso1
- The following thesis describes the design, the synthesis, and the implementation of pulse width modulation (PWM) in Xilinx Field Programmable Gate Array (FPGA). The contribution of this thesis is the development of PWM in Xilinx
monitoringV5
- 文件的FPGA是基于Xilinx ISE写的，所用开发板为zedboard7020 484系列，完成的功能为：读取XADC里的温度，VCC，并存储到RAM中，通过流水灯实现翻看，读取等功能.-Document is based on Xilinx ISE FPGA wrote, the use of development board for zedboard7020 484 series, completed functions: reading XADC in temperature, VC
pipeline_mips_simulation_using_xilinx
- This project is a pipeline simulator using xilinx. All of fetch, decode, execute and write back stages was implemented. That is a nice project for computer architecture course in computer engineering. Good Luck ) -This project is a pipeline simul
cfcard
- 这是xilinx v2开发板cf卡读图片的程序。用c语言编写。在xilinx官方网站上有cf可读图片的工程，再将这段代码加载进去就可以了。这是个调试成功的程序。-This is a development board xilinx v2 picture cf card reading process. With c language. In the Xilinx website have cf readable picture works, then the code is loaded int
test8
- xilinx工程文件，test8.v是源代码，实现了逐位进位的加法器、减法器，和逻辑运算功能。运行通过，仿真成功。-Xilinx engineering documents, test8. V is the source code, to achieve the cascaded carry adder, subtracter, and logical operations function. Running through, the simulation is successful.
xilinx_ddr_verilog
- xilinx赛灵思的DDR控制器源码（包括仿真与说明文档），DDR为mt46v4m16。-Xilinx DDR controller source code (including simulation and documentation), DDR is mt46v4m16.
Asynchronous_FIFO
- 异步FIFO代码，虽然是一个比较简单的程序，但有助于我们更好的理解异步FIFO-This implementation is based on the article Asynchronous FIFO in Virtex-II FPGAs writen by Peter Alfke. This TechXclusive Xilinx website. It has some minor modifications.
a_sum_b
- this is a 2 bit adder for xilinx with ise 9.2
divideer_2
- this is a 2 bit divider for xilinx whit ise 9.2
ram_4_4
- this is a 2 bit ram for xilinx whit ise 9.2
Taximeter
- 出租车计价器（其中包括分频模块，计程模块，计时模块，计费模块，显示模块以及顶层模块），基于Verilog HDL语言，开发板是FPGA(Sparten 6 LXS45),开发环境是Xilinx。-Taxi meter (including frequency module, the meter module, timing module, billing module, display module and top-level module), based on Verilog HDL lang