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myuart
- 使用verilog语言编写的异步串口模块，带有16级深的FIFO，它与DSP28335的SCI相似，可以帮助初学者更快地理解FPGA和DSP的硬件结构和编程思路-Use verilog language of asynchronous serial port module, FIFO with deep level 16, it was similar with DSP28335 SCI, can help beginners to understand faster the FPGA and
tst8
- verilog编写的键盘接口程序，带串口测试-verilog prepared by the keyboard interface program with serial test
bit4_4
- 用verilog语言编写的串口通信程序， 可以和下位机其他串口通信，控制4位继电器的开关-Using verilog language serial communication program, and slave other serial communications, control four relays switch
bit4_8
- 用verilog语言编写的串口通信程序， 可以和下位机其他串口通信，控制8位继电器的开关-Using verilog language serial communication program, and slave other serial communications, control eight relay switches
chenyu--chengxu
- 用verilog语言编写的串口通信程序,可以作为一个地址选择控制器使用，实现和不同的串口设备通信-Using verilog language serial communication program, can be used as an address selection controller, implementation and communication of different serial devices
scommtest
- 串口通信，利用verilog语言能够很好的实现串行通信-Serial communication, use verilog language can achieve the serial communication
uart
- 用verilog写的程序实现串口通信， 用verilog写的程序实现串口通信， -the program is based on verilog, and it s fuction is comunicate with uart
uart_latest.tar
- VERILOG串口IP核，在XC2S200E测试过-UART IP CORE
uart_tx
- 硬件描述语言设计的串口发送源代码UART TX SOURCE CODE-Verilog HDL UART TX RTL SOURCE CODE
UART_RX
- 232串口源程序 verilog实现，频率可调 接受部分-RS232 verilog
UART_TR
- rs232串口通信 verilog代码 发射部分-RS232 verilog
FPGA6_LCDaUART
- 基于FPGA Verilog LCD显示串口数据-Based on the FPGA Verilog LCD display serial data
rec
- 串口接收Verilog程序，可通过参数设置波特率，采用16倍采样方法，稳定可靠，可做为模块直接在顶层例化。-Serial receive Verilog procedures, through parameter setting the baud rate, using 16 times the sampling method, stable and reliable, can be used as module directly instantiated at the top level.
UART
- 本代码用verilog语言配合sopc和nios实现了串口调试的目的。软件编程用C语言描述，只是比较简单的例子，适合初学者做了解用，本人亲自在EP2C8Q上实践。-The code to use verilog language sopc and nios achieved with serial debugging purposes. Software programming using C language descr iption, but relatively simple exampl
uart_verilog
- UART串口通信代码，FPGA编程，用Verilog代码编写-UART serial communication code, FPGA programming with Verilog coding
Example-b3-1
- Verilog/VHDL源码的串口示例，“Altera设计基础篇”第3章的串口示例，包括源码和仿真文件等-Verilog/VHDL source serial example, " Altera Design Basics" in Chapter 3 serial examples, including source code and simulation files, etc.
rs232
- rs232串口通信实验4位的串口，verilog源代码。-rs232 serial communication experiment 4 serial, verilog source code
HY57V64_control
- 本代码用verilog而不是直接在nios中用ip核来实现HY57V641620FTP-6的读写，时序完全正确，从串口输出来验证的数据完全正确。附带说明和参考资料。希望对您有帮助。-This code is used instead of directly in verilog ip core nios used to achieve HY57V641620FTP-6 reading and writing, the timing exactly right, from the serial d
uart
- 基于FPGA的UART程序设计，VERILOG HDL语言编写，可实现串口通信，波特率为115200。已通过串口调试助手验证。-FPGA-based UART program design, VERILOG HDL language, enabling serial communication baud rate to 115200. Has been verified through the serial debugging assistant.
EX7
- 一个基于verilog的串口接收发送模块，可与上位机通信。-One based on the serial receiver sends verilog module can communicate with the host computer.