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mult
- 自己编写的乘法器 二进制4*4 vhdl环境 仿真通过-On time-multiplier binary imagecut.rar 4* 4 VHDL environmental simulation through
vhdl
- 4位乘法器 vhdl library IEEE use IEEE.std_logic_1164.all entity one_bit_adder is port ( A: in STD_LOGIC B: in STD_LOGIC C_in: in STD_LOGIC S: out STD_LOGIC C_out: out STD_LOGIC ) end one_bit_adder -4-bit multipl
24x24-booth
- 可用的24位x24位的booth乘法器的verilog代码-24X24 booth muplily
Four-multipliers-with-VHDL-
- 用VHDL实现四位乘法器，不直接用乘法实现。该代码思路清晰，希望可以帮助到大家！-Four multipliers with VHDL implementation, not directly with the multiplication implementation. The code is clear thinking, I hope to help to you!
95637012Multiplier
- 一种可以完成16位有符号／无符号二进制数乘法的乘法器。该乘法器采用了改进的booth算法，简化了部分积的符号扩展，采用Wallace树和超前进位加法器来进一步提高电路的运算速度。本乘法器可以作为嵌入式CPU内核的乘法单元，整个设计用VHDL语言实现。- This file contains all the entity-architectures for a complete-- k-bit x k-bit Booth multiplier.-- the design makes use of
multiplierunit
- VHDL/FPGA/Verilog 实现乘法器的功能-use VHDL/FPGA/Verilog multiplier unit
mult
- 4比特乘法器的vhdl实现，含modelsim测试文件-4-bit multiplier vhdl implementation, including the test file modelsim
RS_
- RS_255_223_码中乘法器的设计RS_255_223_ code in the multiplier design-RS_255_223_ code in the multiplier design
ATMEGA128
- – 133 条指令 – 大多数可以在一个时钟周期内完成 – 32 x 8 通用工作寄存器 + 外设控制寄存器 – 全静态工作 – 工作于16 MHz 时性能高达16 MIPS – 只需两个时钟周期的硬件乘法器---133 Instruction- most can be completed in one cycle- 32 x 8 General Purpose Working Registers+ Peripheral Control Registers- Fully Stat
butterfly1
- FFT 蝶形处理器的VHDL代码，由一个加法器，一个减法器和一个实例化为组件的旋转因子乘法器ccmul组成-FFT butterfly processor VHDL code by an adder, a subtracter, and an instance of the component into the composition of the rotation factor multiplier ccmul
mux1
- 利用verilog编写的一个乘法器，没有仿真，应该是对的。-this is a verilog cheng xu， cheng fa qi。mei you fang zhen
4bit_multiply
- 4位无符号乘法器，在fpga开发板上实现了乘法的功能-4 unsigned multiplier, in the fpga development board to achieve a multiplication of functions
MULT8
- 用移位相加的算法实现了8位乘法器，文档包含程序，并有详细分析过程-Shift algorithm with the sum of the 8-bit multiplier, the document contains procedures, and detailed analysis
VHDL
- 基本的VHDL程序代码，如加法器，乘法器，译码器，编码器等等，希望能给大家一些帮助，分享万岁！-Basic VHDL code, such as adders, multipliers, decoders, encoders, etc., I hope to give you some help, to share long live!
3.1
- 加法树乘法器带testbench好用的工程-Adder tree multiplier with testbench-use project
3.2
- 查找表乘法器带testbench好用的工程-Easy to use look-up table multiplier works with testbench
3.3
- 布尔乘法器带testbench好用的工程啊-Boolean multiplier works with testbench nice ah
3.4
- 移位除乘法器带testbench好用的工程-Useful addition to the shift multiplier works with testbench
mult
- 4级流水乘法器，本文利用FPGA完成了基于半加器、全加器、进位保留加法器的4比特流水乘法器的设计，编写VHDL程序完成了乘法器的功能设计，并通过Modelsim进行了仿真验证。-Four water multipliers, this paper complete FPGA-based half adder, full adder, carry-save adder 4 bit pipeline multiplier design, write VHDL program to complete
shift_mult_4
- 四位移位乘法器 VHDL 代码 已验证，可以直接拿来用-Four shift multiplier VHDL code has been verified, can be directly used