加法器的VHDL源码及其对于的仿真Testbench 文件的编写-VHDL Code about adder for the "Simple Test Bench" example VHDL Code about adder for the "Simple Test Bench" example

四位逐次进位加法器的verilog实现。附tb.v文件。单片机开发，数字逻辑与处理器基础实验-Four successive carry adder verilog implementation. Tb.v attached file. SCM development, digital logic and processor basic experiment

加法器tb文件，用与对加法器进行仿真处理，通过modusim运行，适合新手参考。(add tb file and with the adder simulation processing, through the modusim run, suitable for novice reference.)