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multiple
- 介绍了几种常用的乘法器的设计，carry_save_mult，ripple_carry_mult等，压缩包中包含结构流程图，用verilogHDL语言，采用modelsim仿真验证
chap8
- 常用经典典型电路，如全加器，乘法器，如何减小资源
multiply
- Verilog hdl语言 常用乘法器设计，可使用modelsim进行仿真-Verilog hdl language commonly used multiplier design, can use the ModelSim simulation
multiplexer
- 几种常用乘法器的Verilog、VHDL代码-Several common multiplier Verilog, VHDL code
c16_multiple
- 精通verilog HDL语言编程源码之2--常用乘法器设计-Proficient in verilog HDL source language programming of 2- Common Multiplier
adder17
- 实现17位加法，利用一个16位超前进位加法器和一个一位全加器构成的一个有进位输入和进位输出的17加法器，并且16位加法器利用的使四位超前进位加法器构成。它在booth乘法器设计中经常用到。可以使初学者对模块的调用了解更加透彻。-Adder 17 to achieve the use of a 16-bit CLA, and a one-bit full adder composed of a binary input and binary output of the adder 17, and
Common_multiplier_verilog_design
- 上传文件为：常用乘法器verilog设计.rar-Upload files as follows: common multiplier verilog design. Rar
fourkindmultiply
- 给出了几种常用乘法器的设计代码 ，读者通过比较可以得出乘法器的设计方法-Given the design of several common multiplier code, the reader can be drawn by comparing the design method of multipliers
plus
- 一个简单的乘法器，实现Activity间的转换以及常用控件的使用-A simple multiplier to achieve the conversion between Activity and the use of common control
chengfa
- 一个简单的android乘法器，实现多个Activity间的跳转以及常用控件的使用-The android a simple multiplier, to jump between multiple Activity and use of common control
verilog_Common_arithmetic
- 常用逻辑运算，加法器，乘法器及除法器的verilog语言，可用modelsim或Quartus II 9.0环境-Common logic operation, adder, multiplier and divider verilog language, can be used modelsim or Quartus II 9.0 environment
multiple
- 常用的乘法器Verilog程序，包括原理图和仿真图片。-Verilog multiple
common-mul
- 常用乘法器设计,有详细的步骤-Common multiplier design；
Chapter16-Multiplier
- 书籍《精通Verilog HDL语言编程》中第16章的程序实例代码，是关于常用乘法器的设计的，对于初学者有一定的帮助-Book "Proficient in Verilog HDL language programming" in Chapter 16 of the procedure code, the common multiplier designed for beginners will certainly help
N-bits-by-M-bits
- 这是一个verilog代码实现的常用乘法器。设计的是通用N比特乘M比特的二进制乘法器-This is a common multiplier verilog code. Design of a generic N bits by M bits of the binary multiplier
Common-multiplier-design
- 常用乘法器设计，用FPGA能实现，值得下载。-Common multiplier design, FPGA can achieve, it is worth downloading.
multiply_verilog
- 几个常用的乘法器的verilog实现，包括普通乘法器，时序乘法器，行波乘法器-Several commonly used multiplier verilog achieve, including ordinary multiplier, multiplier timing, traveling wave multiplier, etc.
fpga_DESIGN_examples
- 自己收集的常用的FPGA模块设计，大家分享啊 异步FIFO设计/伪随机序列应用设计/积分梳状滤波器(CIC)设计/伽罗华域GF（q）乘法器设计/除法器设计/常用加法器设计/常用乘法器设计/RS(204,188)译码器的设计/CORDIC数字计算机的设计-Common FPGA module design your own collection, to share ah Asynchronous FIFO design/application design pseudo-random s
常用乘法器设计
- 采用Verilog语言设计的几种常用乘法器。(several multiplier designed by verilog)