搜索资源列表
VHDL
- 基于VHDL状态机设计的智能交通控制灯VHDL程序-VHDL-based state machine design of intelligent traffic control lights VHDL procedures
sdram_vhdl_lattice
- sdram接口的vhdl实现,适用于lattice的FPGA，内含状态机和各个模块的具体实现-SDRAM interface VHDL realization lattice applied to the FPGA, containing the state machine and the concrete realization of each module
4bit_buma_adder
- Verilog作业 ：自己写的源码输入，补码输出的，由状态机控制的四位加法器，为保证时序，加法器模块为超前近位加法器，包含测试台，通过 Modelsim 、Synplify仿真。-Verilog operation: the source code to write their own input, complementary code output by the state machine to control the four adder, in order to ensure timing
EDA
- 地址译码，状态机的编写，三态输出，布司乘法器-Address decoder, the preparation of state machines, three-state output, cloth Division Multiplier
vhdl_case
- 这是一个两个状态机的文件 都是很输入有关的 是我很我的同学的 希望对大家还是有点帮助的 -This is a two state machine documents are related to the importation of my classmates I hope all of you a little help
howwite_status_machine_with_Verilog
- 如何用verilog语言写好状态机的不错的文档，希望对大家有所帮助-How to use Verilog state machine language to write good documentation, I hope all of you to help
i2c
- 一个用状态机VHDL语言编写的I2C源代码-A state machine by VHDL language I2C source code
zzx
- 这个并串转换代码是依靠同步状态机来实现其控制的。其实并串转换在实际的电路中使用还是比较多的，尤其在通信线路方面的复用和分解方面，原理上就是一个串并转换和并串转换的过程。举个简单的例子，计算机串口发送数据的过程，如果满足发送条件了，其实就是一个并串转换的过程了。好了，废话不说，看代码就是。 写完一看，一个并串转换居然搞了这么大，有点失败。但是整个代码已经通过了后仿真，而且思路还是比较清楚的，可靠性和稳定性方面也应该没有问题滴，呵呵。不过说老实话，里面有些信号是确实可以去掉的，不过后来就懒
state_machine
- 三进程有限状态机的设计程序，内附有AD574逻辑控制真值表以及采样状态机的原理图-Third, the process of finite state machine design process, logic control of typhoons and rainstorms are AD574 truth table, as well as sampling state machine schematic
diyabiao
- moore状态机~~~ 用vhdl语言实现-moore state machine ~ ~ ~ using VHDL language
gkermit-1.0-1.src
- 红帽版linux下串口通讯kermit文件传输协议简单版源码.想学习kermit的可以看看,里面关于状态机用的比较精彩.先解压成rpm,再在linux下解压.-Red Hat linux version of serial communication under the kermit file transfer protocol simple version of source code. Want to learn kermit can take a look at, which on the
MyState
- 这份是实验课上的教师和学生用的实例。关于用matlab simulink仿真状态机并生成vhdl代码的详细内容-The experimental class teachers and students to use examples. Matlab simulink simulation on the use of state machine and generates VHDL code details
moore
- moore状态机用VHDL语言进行实现 -moore state machines using VHDL language to achieve
qudou
- 通用的基于状态机的VHDL按键及信号去抖动模块，非常有用-Generic VHDL-based state machine keys and signal to the jitter module, very useful
milixingzhuangtaiji
- 米立型状态机的输出变化要提前一个周期，即一旦输入信号或状态发生变化，输出信号立刻发生变化。-M-li-type state machine to advance the output changes in a cycle, that is, once the input signal or status change, the output signal of immediate change.
state_seg
- xilinx3s400开发板厂家光盘带源码。state状态机、reg-CD-ROM manufacturers xilinx3s400 development board with source code. state state machine, reg
VHDL
- 状态机及其VHDL设计,详细介绍了状态机的基本结构、功能和分类，以及有限状态机的一般设计思路与方法、状态机编码方案的恰当选取、Moore和Mealy状态机的本质区别及设计实现-State machine and the VHDL design, described in detail the basic structure of state machines, function and classification, as well as finite state machine of the
S_MACHINE
- 状态机的基础,实现状态之间的转换,四个状态在不同情况的转换功能-The basis of state machine to achieve a state of transition between the four different situations in the state of the conversion function
(Mealy)
- 状态机的基础,实现状态之间的转换,四个状态在不同情况的转换功能-The basis of state machine to achieve a state of transition between the four different situations in the state of the conversion function
doc
- VHDL：用状态机的方法实现一个8位乘法器-VHDL: state machine method used to achieve an 8-bit multiplier