搜索资源列表
weitongbu
- 用数字锁相环实现位同步信号提取,包含各个模块的电路设计程序。-To achieve bit synchronization with digital phase-locked loop signal extraction, each module contains the circuit design process.
dlia_pro
- 比较快速的正交解调算法,在TMS320LF2407上实现,使用语言C语言,内有论文《一种新型数字锁相放大器的设计及其优化算法》,可以软件实现检测相位差。-Comparison of fast orthogonal demodulation, in TMS320LF2407 to achieve, using the language C language, there are paper, " a new type of digital lock-in amplifier design
frerecov
- 通信系统中有关于利用锁相环完成载波跟踪恢复的仿真功能-Communication system using phase-locked loop on the completion of the simulation function to restore the carrier tracking
linux
- Linux下的编程 本人课程设计 全部能运行 包括:合并排序.cpp 进程管理.cpp 进程控制实验.c 内存管理.cpp 生产者和消费者.c 死锁实验.c 线程实验.c-Programming under Linux I can run all the curriculum include: Merge sort. Cpp process management. Cpp process control experiment. C memory management. Cpp producers
pllmatlab
- 锁相环的一些MATLAB的仿真程序,下载了看看,觉得蛮有用,顺便用来下载东西用-pll matlab
vbaProjectPlusUnlockingDevice
- vba工程加解锁器 vba工程加解锁器-vba project plus unlocking device unlock the device vba vba project plus project plus unlocking device
pll_sim
- 这是一个根据锁相环原理编写的MATLAB仿真程序,内有详细注释,同时附带了仿真结果图。-It is MATLAB simulation program of phase locked loop,while with the simulation results Fig.
VC_hook_lock_screen_systems_achieve_program_source
- VC实现挂机锁屏系统程序源码VC hook lock screen systems to achieve program source code-VC hook lock screen systems to achieve program source code
Digitalpower
- 单片机设计了一种单片锁相倍频电 路,利用片内定时器和数字算法实现了对输入信号的同步 锁相和倍频,并输出倍频信号-: A single- chip digital phase- locking frequency- multi- plier circuit is designed based on the AT89c2051.The circuit can track the input signal in- phase and output the frequency- mu
DESKLOCK
- 简单挂机锁(开源),Delphi环境下实现其功能。-desk lock
Matlabpll
- 基于Matlab的数字锁相环的仿真设计,一篇毕业论文,对数字和模拟锁相环进行了详细的分析和仿真-Matlab-based simulation of digital PLL design, a thesis on digital and analog phase-locked loop for a detailed analysis and simulation
PLLC
- 本程序利用平方环实现载波同步,使用锁相环进行跟踪相位偏移-This program makes use of the square ring to achieve carrier synchronization, with the use of PLL to track the phase shift
DesignoftrackingloopofGPSsoftwarereceiver
- 本文在分析GPS 软件接收机跟踪原理的基础上,首先比较码环与载波环不同鉴相器的性能,然后对二阶锁相环中不同环路参数设下的跟踪效果进行仿真分析,最后设计 了合适的码环与载波环路,并用实际采集的GPS 数据论证了所设计环路的有效性,为GPS 软件接收机跟踪环路的设计提供了参考。-Based on the analysis of GPS receiver tracking software on the basis of the principle, first compare the diffe
AD-PLL
- 基于VHDL的全数字锁相环的设计与实现,quartusII的仿真程序。-DPLL based on VHDL Design and Implementation, quartusII the simulation program.
LOCK
- vc++的挂机锁屏系统,相信这个大家都不陌生吧,可以锁定你的计算机,别人无法操作,需要知道口令才可以,S本软件不但功能完善,而且界面友好,仿QQ的界面,CcTry.Com截图所示,还会适时弹出操作提示,更加人性化,可以专用于网吧或个人办公计算机,开始挂机后,显示挂机时间,而且还可以用屏幕键盘输入密码和隐藏窗口(类似QQ),本程序还涉及一些注册表的操作,当关闭本程序时,会释放注册表。 -vc++ to hang up the lock screen system, I believe that
84f704a6df6c
- 介绍数字锁相环的基本结构,详细分析基于FPGA的数字锁相环的鉴相器、环路滤波器、压控振荡器各部分的实现方法,并给出整个数字锁相环的实现原理图。仿真结果表明,分析合理,设计正确。-MC145159 PLL frequency synthesizer design and realization of PLL frequency synthesizer the basic principles of integrated PLL chip M C 145159 work characteristic
vhdl3
- 介绍一种基于VHDL 语言的全数字锁相环实现方法, 并用这种方法在FPGA 中实现了全 数字锁相环,作为信号解调的位同步模块。-Introduction of a language based on VHDL implementations of DPLL, and this method is implemented in the FPGA digital phase locked loop, as the signal demodulation of bit synchronizatio
Androidpingbao
- Android 手机上用的屏幕保护程序,Java源码,具备锁屏、屏蔽home、屏蔽返回、屏蔽挂机键等功能,研究新型的Android系统,是手机操作系统的又一方向。通过这些小而实用的系统开发,帮助你对Android系统开发有个更全面的了解。 -Android phone screen saver with, Java source code, with the lock screen, shielded home, shield back, shielding hold button and
pll
- 用matlab模拟仿真锁相环,一个很好的程序,希望能帮到你-PLL with matlab simulation, a very good program, hope you can help
Phase-locked-loop
- 该程序是锁相环的MATLAB的简单实现程序,从中可以看到锁相环的基本功能的实现。-This program is a simple phase locked loop of MATLAB implement programs, from which you can see the basic function of phase-locked loop of implementation.