搜索资源列表
booth.rar
- 一个基于VerilogHDL语言的16位的booth算法的乘法器及其测试代码,VerilogHDL language based on the 16-bit multiplier of the booth algorithm and test code
mult16s
- 16位乘法器，VHDL语言编写的，供大学交流学习-16-bit multiplier
mult16
- 基于wallance树的16位乘法器，程序是用verilog写的，经测试好用，对初学者有很大的帮助-16-bit multiplier, based on wallance tree program is written with verilog test handy for beginners great help
cmultip
- 用VERILOG HDL 实现节省乘法器的16位复数乘法器-With VERILOG HDL achieve savings of 16-bit complex multiplier multiplier
ls12_mux16
- 一个16位乘法器的veriolog语言实现。使用初学着。-A 16-bit multiplier veriolog language. Use a novice.
adder17
- 实现17位加法，利用一个16位超前进位加法器和一个一位全加器构成的一个有进位输入和进位输出的17加法器，并且16位加法器利用的使四位超前进位加法器构成。它在booth乘法器设计中经常用到。可以使初学者对模块的调用了解更加透彻。-Adder 17 to achieve the use of a 16-bit CLA, and a one-bit full adder composed of a binary input and binary output of the adder 17, and
16_bit
- 采用boot算法的16位乘法器,速度较快，可以试下哈-Boot algorithm using 16-bit multiplier, faster, you can try under the Kazakhstan
16bit_mult
- 16位的无符号数乘法器，自己写的，经得起验证，注释很详细-16-bit unsigned multiplier, its own written
wallace
- wallace tree 用于16位乘法器的verilog 的 wallace tree代码 -wallace tree verilog file. 16bit wallace tree adder.
mux
- 本例实现的功能是一个16位的乘法器，并增加了仿真代码-In this case the function is to achieve a 16-bit multiplier, and to increase the simulation code
Muliply
- 16-bit multiplier in VHDL
MUX16
- 基于VerilogHDL的简易的16位以为累加乘法器，包括乘法器模块和测试模块，已经通过仿真测试。-Based on the simple VerilogHDL that the cumulative 16-bit multiplier, including the multiplier module and test module has been tested by simulation.
chengfaqi
- 基于FPGA采用时序逻辑方法设计的16位乘法器代码-FPGA-based temporal logic designed using 16-bit multiplier code
mult
- 用verilog HDL语言实现的16位乘法器，以及tesrbench（测试文件）。-Verilog HDL language with 16-bit multiplier, and tesrbench (test file).
16-bit-parallel-mult
- 16位并行乘法器， 由四个4位乘法器组成-16-bit parallel multiplier, consisting of four four multipliers
Verilog-code-for-multiplier
- VERILOG CODE FOR 16 BIT MULTIPLIER USING MODIFIED BOOTH ALGORITHM
original-1-by-16-bit-multiplier
- 原码一位乘16位乘法器 用VerilogHDL语言实现-Original code A by 16-bit multiplier VerilogHDL language used to achieve
16bit-multiplier
- 实现verilog16位乘法器，verilog新手(achieve 16-bit multiplier)
booth
- 基于booth算法的16位乘法器，通过减少部分积的运算次数提升速度。(The 16 bit multiplier based on the Booth algorithm improves the speed by reducing the number of arithmetic times of the partial product.)
16 bit signed number multiplier
- 16位有符号数乘法器，使用Booth编码和华莱士树，提供程序源文件和测试文件(The 16 bit signed multiplier uses Booth encoding and Wallace tree to provide source files and test files.)