搜索资源列表
aes
- aes的加密解密算法的源代码以及测试源代码和仿真结果图-aes encryption decryption algorithm source code and test source code and simulation results map
aescore
- 基于FPGA的AES算法实现的VERILOG源代码，对于信息安全专业研究AES算法的硬件实现很有用-FPGA-based AES algorithm implementation VERILOG source code, for the information security professional research of the hardware implementation of AES algorithm is useful
FPGA
- 此课件是基于FPGA的加密芯片设计实例，DES的FPGA实现，包括DES加密算法简述，DES的伪代码描述，设计流程，运算电路模型设计，算法程序设计 -The courseware is based on the FPGA chip design example of encryption, DES for FPGA implementation, including the DES encryption algorithm briefly, DES pseudo-code descr ipt
CoreAES128
- Full AES Simulation Code
mini_aes_latest[1].tar
- AES 加解密 代码, 有文档说明，testbench-AES encoding decoding source code in HDL
AES
- This the source code of AES algorithm which is used in network security.-This is the source code of AES algorithm which is used in network security.
63535312DCTofJPEG
- 用verilog代码实现JPEG压缩编码过程中的DCT模块，用移位加法实现了乘法-Verilog code using JPEG compression encoding process to achieve the DCT module, with the shift to achieve the multiplication addition
systemcaes_latest.tar
- 高级加密标准aes加密算法用fpga实现的Verilog源代码。-Advanced encryption standard aes encryption algorithm using fpga implementation Verilog source code.
aes_crypto_core_latest.tar
- verilog code for aes
aes
- Matlab code to simulation the wireless channel type.This is the most common case called Rayleigh channel.And in the frequency selective channel.
aes_thesis_v1.0
- AES VERILOG CODE 128 192 32DES比較-AES VERILOG CODE 128 192 32DES Comparison
LIP1611CORE_AES128_SEC_UWB
- AES 128 Synthesisable RTL code
AES!
- AES algorithm very good code tested in xilinx ise tool
sbox
- verilog code for s-box generation for AES algorith
09912007AEScoremodules
- aes descr iption architecture processes vhdl code with pipelining and throughput reduction with an aim to create a faster AES decoding system in FPGA
aes-vhdl
- this file contains vhdl code for aes
Advanced-Encryption-Standard-(AES)
- AES decryption standards, vhdl code
aes_imp
- AES CODE IN VHDL FOR ENCRYPTION AND DECRYPTION
aes_thesis_v1.0
- aes code in verilog vhdl language which is very useful.
aes-master
- aes master by vhdl code and decode