搜索资源列表
VHDL-based-taxi-meter
- 本源码介绍了一种出租车计价器的设计方案，并且是基于VHDL语言，可以轻松在FPGA/CPLD上实现-This source presents a taxi meter design, and is based on the VHDL language, you can easily in the FPGA/CPLD to realize
MUXplus2
- Max+plusⅡ是Altera公司提供的FPGA/CPLD开发集成环境，Max+plusⅡ界面友好，使用便捷，被誉为业界最易用易学的EDA软件。本资源分七节内容详细的讲解了MUX+PLUSⅡ软件的操作及应用。-Altera Max+ plus Ⅱ is provided by FPGA/CPLD development integration environment, Max+ plus Ⅱ friendly interface and easy to use, known as the ED
CPLDFPGAprog
- vdhl programming notes for cpld and fpga
Altera-FPGA_CPLD
- FPGA CPLD 高级篇 教你怎么编verilog-FPGA CPLD senior articles teach you how to compile verilog
CPLDMod2
- CCD 驱动控制程序 基于CPLD 多项执行-CCD drive control program is based on a number of FPGA implementation
FIR_filter
- Parallel FIR filter example. It is low-pass filter for CPLD or FPGA platforms. Project compiled and simulated in Modelsim
vgaverilog
- 本程序实现了基于FPGA/CPLD的VGA显示设计，简单易懂，可以输出8种颜色，即3位RGB颜色，共8种组合。连接FPGA的VGA口和液晶等显示器即可观察实验现象。-This procedure implemented based on FPGA/CPLD' s VGA display design, easy to understand, you can output 8 colors, the three RGB colors, a total of 8 combinations. FPGA
Linux-driver-development2
- 作者：华清远见嵌入式学院。《Linux设备驱动开发详解》（08&09年度畅销榜TOP50）第2章、驱动设计的硬件基础。本章讲解底层驱动工程师必备的硬件基础，给出了嵌入式系统硬件原理及分析方法的全景视图。2.1节讲解微控制器、微处理器、数字信号处理器以及应用于特定领域的处理器各自的特点。2.2节对嵌入式系统中所使用的各类存储器与CPU的接口、应用领域及特点进行了详细讲解。2.3节讲解常见的外设接口与总线的工作方式，包括串口、I2C、USB、以太网接口、ISA、PCI和cPCI等。嵌入式系统硬件电路
27899801
- programming CPLD and FPGA Code
Dcufaqi
- hdlthis is a FPGA and cpld good this a FPGA and cpld good-this is a FPGA and cpld goodthis is a FPGA and cpld goodthis is a FPGA and cpld good this is a FPGA and cpld good this is a FPGA and cpld good
FPGA_Designdiscrinple
- FPGA/CPLD 数字电路设计经验分享，来源别人的经验和设计技巧。-FPGA/CPLD digital circuit design experience to share, the source of experience and design skills of others.
FPGA_CPLD
- FPGA/CPLD数字电路设计经验分享,内容包括数字电路设计的一些经验。-Sharing the experience of designing digital circuit with FPGA/CPLD
shouchishiboqi
- 手持式存储示波表中的数据采集设计。以ARM和单片机为主辅，FPGA/CPLD为逻辑平台-Handheld storage oscilloscope table data acquisition design. ARM-based microcontroller and secondary, FPGA/CPLD logic platform
FPGACPLD
- fpgA和cpld的概述及芯片内部结构介绍。-fpgA and cpld overview and introduce the internal structure of the chip.
sin_10M
- FPGA/cpld 产生步进为1Hz的正弦波,最大为10M,使用的晶振为50M -FPGA/cpld generation step of 1Hz sine wave, up to 10M, 50M crystal oscillator for use
IntroductionPtoPCPLDPandPFPGAPDesign
- Introduction to CPLD and FPGA Design
Altera
- VHDL verilog fpga cpld-DIGITAL
ALTERA_CPLD_and_FPGA_device08_09_27-
- 第4章ALTERA的CPLD与FPGA器件08_09_27嵌入式编程系列-Chapter 4 ALTERA CPLD and FPGA devices in embedded programming series 08_09_27
Frequency-counter
- 基于FPGA的频率计设计。通过FPGA运用、 HDL编程，利用FPGA(现场可编程门阵列)芯片设计了一个8位数字式等精度频率计，该频率计的测量范围为0-100MHZ，利用QUARTUS II集成开发环境进行编辑、综合、波形仿真，并下载到CPLD器件中，经实际电路测试，仿真和实验结果表明，该频率计有较高的实用性和可靠性。-Frequency counter FPGA-based design. By using FPGA, VHDL programming, the use of FPGA (fi
debounce_1_Sch
- 用QuartusII原理图形式编写的按键消抖程序,分频产生100Hz的按键采样时钟,采样时钟周期为10ms, 按键按下的时间与产生低电平信号的时间相等,按键按下的时间与LED灯亮的时间相等-*Project Name :debounce_Sch *Module Name :debounce_Sch *Target Device :Any Altera FPGA/CPLD Device *Clkin : 50MHz *Desisgner : zhaibin *D