搜索资源列表
Verilog_div_frequency
- 本文使用实例描述了在 FPGA/CPLD 上使用 Verilog进行分频器设计，主要包括50 占空比的奇数分频. -This article uses the example describes the crossover design using Verilog in FPGA/CPLD, including the 50 duty cycle odd divider
dotmatrix_8x16-VHDL
- Drive a 8x16 Dotmatrix LED Display By CPLD or FPGA
VGA
- THIS CODE VERY GOD FOR DRIVE VGA IN CRT MONITOR WITH CPLD AND FPGA
FFlash_FPAG_JP
- FPGA或者CPLD通过JTAG接口口对FLASH进行读写的资料。非常有用 -FPGA or CPLD through the JTAG interface port on the FLASH read and write information. Very useful
CoolRunner
- This the default CPLD design shipped with the board. The CPLD helps reduce the number of jumpers on the board and simplifies the interaction of all the possible FPGA configuration memory sources-This is the default CPLD design shipped with the board.
Example-8-1
- 我的观点是Verilog和VHDL对于高手而言各有利弊，Verilog感觉更适合于RTL（寄存器传输级）的描述，而VHDL更适于System级的建模。 但是初学者强烈建议学习Verilog，更容易入手些，但是学习过程中一定要注意下面一点，毕竟国内外大公司现在大都采用Verilog是有其原因的。 l FPGA/CPLD、ASIC的逻辑设计所采用的硬件描述（HDL）语言是同软件语言（如C，C++等）是有本质区别的！虽然Verilog很多语法规则和C语言相似，但是Verilog是硬件描述
FPGAorCPLD_vga_Principle
- 介绍了FPGA或者CPLD上VGA显示的基本原理，这是一份很好论文说明。保证你值得拥有。-Describes the basic principles of the VGA display on the FPGA or CPLD, which is a very good paper describes. You deserve.
minicpu(compiler-8bit)
- CISC microprocessor IP core & 8 bit compiler, verilog语言编写，可在FPGA和CPLD上综合实现,结构类似Intel 8085-CISC microprocessor IP core and 8-bit compiler, verilog language, FPGA and CPLD comprehensive realization .structure is similar to Intel 8085
Xilinx_TFT_serial
- 基于FPGA/CPLD平台的640*480分辨率的TFT-LCD控制器，通过UART口接收外部输入信号-Based platform FPGA/CPLD 640* 480 resolution TFT-LCD controller, an external input signal received through the UART port
IIC_MasterDriver
- IIC主机控制vhdl源码,支持IIC普通和快速模式,多个fpga/cpld平台已验证-IIC host control source code,normal and fast mode support
AlteraPFPGA_CPLD
- FPGA和CPLD的学习资料，从初级到高级，从基础到深入，对于学习FPGA的初学者很有用处。-FPGA and CPLD learning materials, from beginner to advanced, from basic to in-depth for beginners learning FPGA useful.
FPGACPLD-design-tools-Xilinx-ISE
- FPGA/CPLD设计工具──Xilinx ISE使用详解！x详细介绍了XilinxISE的使用方法！-FPGA/CPLD design tools ─ ─ Xilinx ISE explain the use of! x details use XilinxISE!
ise1
- ise教程,Xilinx FPGA/CPLD设计手册 Xilinx公司推荐FPGA/CPLD培训手册-ise for Xilinx FPGA/CPLD
nano-logic
- 本手册适用于使用NANO-LOGIC CPLD 系列开发板的用户。 一款较高端FPGA 开发板既可以做项目开发也可以配上一个“通用的基础设备接口 板”作为新人培训入门使用 本产品的推出旨在于方便用户扩展基础设备和初学者学习使用。在FPGA 产品的设计 中，在初期调试时为了方便调试和显示程序工作状态，经常会用到大量的调试接口，比 如灯、按键、液晶显示等设备；这些设备既浪费有限的FPGA 资源又浪费宝贵的板卡体 积。本开发板提供了通常用户调试程序所需要的基础输入输出和上位机通
VHDL-divider-design
- VHDL分频器设计，本文使用实例描述了在FPGA/CPLD上使用VHDL进行分频器设计，包括偶数分频、非50 占空比和50 占空比的奇数分频、半整数（N+0.5）分频、小数分频、分数分频以及积分分频。-VHDL divider design, this article describes use cases, including even divide, non-50 duty cycle and 50 duty cycle odd divider, half integer (N+0-cr
keyboard
- fpga/cpld按键扫描vhdl语言代码（4x4按键阵列）-Fpga/cpld keypad scanning VHDL language code (4x4 scan)
FPGA_CPLD-SHC
- FPGA_CPLD-SHC多款FPGA CPLD开发板的原理图，很好的线路设计参考-FPGA_CPLD-SHC Variety of FPGA CPLD development board schematics, a good reference circuit design
PARITY-CHECK
- this vhdl code for parity check is very helpful while coding and decoding , Implementing this in an cpld of fpga is very easy and it can be used as a subpart of any embededd design such as multiplexers , Decoders etcv -this vhdl code for parity check
omu_b
- CPLD的功能实现,主要有FPGA配置、寄存器定义、两种分频等内容-The realization of the function of the Slave SerialCPLD, basically have FPGA configuration, register definition, two kind of frequency division, etc
RD1088_rev01.2
- FPGA或CPLD读取SD卡的IP核，基于wishbone接口，支持SDHC2.0，包含了使用说明，为Verilog语言编写-FPGA or CPLD reads the SD card IP core, based on the wishbone interface, support SDHC2.0, contains instructions for the Verilog language