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cpu
- 本程序主要完成cpu的几个主功能模块的开发,开发语言为verilog硬件语言,基本能模拟cpu的核心功能!-The program mainly to complete the main features of several cpu module development, hardware development language for the verilog language, the basic core functionality can simulate the cpu!
CPU
- mips系列,CPU的Verilog语言设计,自己写的-mips series, CPU of the Verilog language design, to write their own
NET2
- This file with the wavelet transf Mallat implementation of wavelet Verilog hdl code modules for radi Modelsim 6.6 crack, can be used f A written using Verilog DDR2 cont Simple CPU VHDL implementation an Dual-port RAM design, usi
LIP3001CORE_cpu
- CPU Verilog Module source code
risc_cup
- 精简指令集CPU的VERILOG语言实现,很有用-RISC CPU the VERILOG language, very useful
DW8051_core
- 8051的内核源码,用verilog HDL写成,已验证功能正确-open core fo 8051 cpu
CPU
- cup developed by scope verilog
CPU
- 用Verilog HDL语言写一个简单的处理器CPU。包括IR,Control unit,A,Addsub,G,Counter,8个寄存器。-Verilog HDL language used to write a simple processor CPU. Including IR, Control unit, A, Addsub, G, Counter, 8 registers.
Verilog-HDLTOP-DOWN
- 用Verilog HDL的建模来设计一个经简化的只有八条指令、字长为一字节的RISC中央处理单元(CPU)的顶层设计。-Modeling with the Verilog HDL to design a simplified and only eight instructions, word length is a byte RISC central processing unit (CPU) of the top-level design.
cpu
- 用Verilog语言编写的单周期cpu,实现的指令有 add,addu,addi,addiu,sub,subu,clo,clz,xori,nor,slt,slti,sltu,sltiu,blez,j.-Verilog languages ??with single-cycle cpu, implementation instructions are add, addu, addi, addiu, sub, subu, clo, clz, xori, nor, slt, slti, sltu,
cpu
- 用verilog描述一个完整的cpu,以完成仿真,仿真结果合理-Complete with a verilog descr iption of the cpu, in order to complete the simulation, the simulation results are reasonable
MIPS_cpu_verilog
- 带流水线的类MIPS CPU verilog源代码-With lines of class MIPS CPU verilog source code
32bit-RISC-CPU-IP
- 使用Verilog语言实现的RISC精简指令集CPU IP核,该CPU具有32位数据宽度,5级流水线结构和指令预判和中断处理功能,适合Verilog语言深入学习者参考。-Using the Verilog language implementation of RISC Reduced Instruction Set CPU IP cores, the CPU has a 32-bit data width, 5-stage pipeline structure and instruction p
Digital-Design-Through-Verilog
- cpu design an intutive approach raja sekhar 08-12
CPU-32
- A 32 bit cpu implementation designed on verilog with test bench.
pipeline_code
- 实现了MIPS五级流水CPU,用verilog语言实现-MIPS CPU verilog
cycle_code
- verilog实现了MIPS多周期(5周期)的CPU-verilog MIPS 5 cylce
pc-matrix
- 简单CPU verilog代码,完全按照COA中描述的结构,是微程序实现-simple structure cpu code, using verilog-HDL, totally struct the organization according to the COA,
risc_cpu-OK
- 夏宇闻 verilog数字系统设计教程源码 第二版,实现了简单的RISC CPU。印刷版有误,已改正。- A simple RISC CPU Verilog HDL source code. Work well.
single-clock-CPU
- 单时钟周期CPU,verilog语言编写,quartusII运行-A single clock cycle CPU